/**
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******************************************************************************
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* @file startup_Xl6600.s
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* @author chipways
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* @version V3.5.0
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* @date 11-March-2011
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* @brief xl6600d High Density Devices vector table for Atollic toolchain.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address,
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* - Configure the clock system
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* - Configure external SRAM mounted on xl6600d board
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* to be used as data memory (optional, to be enabled by user)
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* - Branches to main in the C library (which eventually
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* calls main()).
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* After Reset the Cortex-M3 processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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******************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, CHIPWAYS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2011 CHIPWAYS</center></h2>
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******************************************************************************
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*/
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.syntax unified
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.cpu cortex-m3
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.fpu softvfp
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.thumb
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.align 4
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.global g_pfnVectors
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.global Default_Handler
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.global GPIOA
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.global GPIOB
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.global GPIOC
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.global IRQ
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.global SCB
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.global NVIC
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.global SysTick
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.global SIM
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.global KBI0
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.global KBI1
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.global PIT
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.global RTC
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.global PWT
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.global UART0
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.global UART1
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.global UART2
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.global WDOG
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.global MCAN
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.global ICS
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.global OSC
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.global FTM0
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.global FTM1
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.global FTM2
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.global FMC
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.global I2C0
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.global I2C1
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.global SPI0
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.global SPI1
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.global PORT
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.global PMC
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.global ACMP0
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.global ACMP1
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.global ADC0
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.global CLMA
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.global CLMB
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.global CRC
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.global DMA
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.global EWM
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/* start address for the initialization values of the .data section.
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defined in linker script */
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.word _sidata
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/* start address for the .data section. defined in linker script */
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.word _sdata
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/* end address for the .data section. defined in linker script */
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.word _edata
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/* start address for the .bss section. defined in linker script */
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.word _sbss
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/* end address for the .bss section. defined in linker script */
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.word _ebss
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.equ BootRAM, 0xF1E0F85F
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/**
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* @brief This is the code that gets called when the processor first
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* starts execution following a reset event. Only the absolutely
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* necessary set is performed, after which the application
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* supplied main() routine is called.
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* @param None
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* @retval : None
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*/
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.section .text.Reset_Handler
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.align 4
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r3, =_sidata
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ldr r3, [r3, r1]
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str r3, [r0, r1]
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adds r1, r1, #4
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LoopCopyDataInit:
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ldr r0, =_sdata
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ldr r3, =_edata
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adds r2, r0, r1
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cmp r2, r3
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bcc CopyDataInit
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ldr r2, =_sbss
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/* b LoopFillZerobss */
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movs r1, #0
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b LoopCopyFalshCodeInit
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CopyFlashCodeInit:
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ldr r3, =_falsh_sidata
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ldr r3, [r3, r1]
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str r3, [r0, r1]
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adds r1, r1, #4
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LoopCopyFalshCodeInit:
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ldr r0, =_flash_start
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ldr r3, =_flash_end
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adds r2, r0, r1
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cmp r2, r3
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bcc CopyFlashCodeInit
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ldr r2, =_sbss
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b LoopFillZerobss
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/* Zero fill the bss segment. */
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FillZerobss:
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movs r3, #0
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str r3, [r2], #4
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LoopFillZerobss:
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ldr r3, = _ebss
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cmp r2, r3
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bcc FillZerobss
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/* Initialize the stack pointer */
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ldr r0,=_estack
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mov r13,r0
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/* Call the clock system intitialization function.*/
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bl SystemInit
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/* Call static constructors */
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bl __libc_init_array
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/* Call the application's entry point.*/
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bl main
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bx lr
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.size Reset_Handler, .-Reset_Handler
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/**
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* @brief This is the code that gets called when the processor receives an
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* unexpected interrupt. This simply enters an infinite loop, preserving
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* the system state for examination by a debugger.
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*
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* @param None
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* @retval : None
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*/
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.section .text.Default_Handler,"ax",%progbits
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.align 4
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Default_Handler:
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Infinite_Loop:
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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/******************************************************************************
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*
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* The minimal vector table for a Cortex M3. Note that the proper constructs
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* must be placed on this to ensure that it ends up at physical address
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* 0x0000.0000.
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*
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******************************************************************************/
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.section .isr_vector,"a",%progbits
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.align 4
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.type g_pfnVectors, %object
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.size g_pfnVectors, .-g_pfnVectors
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g_pfnVectors:
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.word _estack
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.word Reset_Handler
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.word NMI_Handler
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.word HardFault_Handler
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.word MemManage_Handler
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.word BusFault_Handler
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.word UsageFault_Handler
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.word 0
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.word 0
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.word 0
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.word 0
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.word SVC_Handler
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.word DebugMon_Handler
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.word 0
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.word PendSV_Handler
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.word SysTick_Handler
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.word Reserved16_IRQHandler
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.word Reserved17_IRQHandler
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.word Reserved18_IRQHandler
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.word Reserved19_IRQHandler
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.word Reserved20_IRQHandler
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.word FMC_IRQHandler
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.word PMC_IRQHandler
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.word DMA_IRQHandler
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.word I2C0_IRQHandler
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.word I2C1_IRQHandler
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.word SPI0_IRQHandler
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.word SPI1_IRQHandler
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.word UART0_IRQHandler
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.word UART1_IRQHandler
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.word UART2_IRQHandler
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.word ADC0_IRQHandler
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.word ACMP0_IRQHandler
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.word FTM0_IRQHandler
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.word FTM1_IRQHandler
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.word FTM2_IRQHandler
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.word RTC_IRQHandler
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.word ACMP1_IRQHandler
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.word PIT_CH0_IRQHandler
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.word PIT_CH1_IRQHandler
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.word KBI0_IRQHandler
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.word KBI1_IRQHandler
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.word Reserved42_IRQHandler
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.word ICS_IRQHandler
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.word WDOG_IRQHandler
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.word PWT_IRQHandler
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.word MCAN_IRQHandler
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.word EXTI0_IRQHandler
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.word EXTI1_IRQHandler
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.word EXTI2_IRQHandler
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.word EXTI3_IRQHandler
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.word EXTI4_IRQHandler
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.word EXTI5_IRQHandler
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.word EXTI6_IRQHandler
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.word EXTI7_IRQHandler
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.word EXTI8_IRQHandler
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.word EXTI9_IRQHandler
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.word EXTI10_IRQHandler
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.word EXTI11_IRQHandler
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.word EXTI12_IRQHandler
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.word EXTI13_IRQHandler
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.word EXTI14_IRQHandler
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.word EXTI15_IRQHandler
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.word EWM_IRQHandler
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.word Reserved21_IRQHandler
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.word BootRAM /* @0x1E0. This is for boot in RAM mode for
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xl6600d High Density devices. */
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GPIOA:
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.word 0x40100000
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GPIOB:
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.word 0x40100040
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GPIOC:
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.word 0x40100080
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IRQ:
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.word 0x40031000
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SysTick:
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.word 0xE000E010
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NVIC:
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.word 0xE000E100
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SCB:
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.word 0xE000ED00
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SIM:
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.word 0x40048000
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KBI0:
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.word 0x40079000
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KBI1:
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.word 0x4007A000
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PIT:
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.word 0x40037000
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RTC:
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.word 0x4003D000
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PWT:
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.word 0x40033000
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UART0:
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.word 0x4006A000
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UART1:
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.word 0x4006B000
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UART2:
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.word 0x4006C000
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WDOG:
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.word 0x40052000
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MCAN:
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.word 0x40024000
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ICS:
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.word 0x40064000
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OSC:
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.word 0x40065000
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FTM0:
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.word 0x40038000
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FTM1:
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.word 0x40039000
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FTM2:
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.word 0x4003A000
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FMC:
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.word 0x40020000
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I2C0:
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.word 0x40066000
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I2C1:
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.word 0x40067000
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SPI0:
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.word 0x40076000
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SPI1:
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.word 0x40077000
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PORT:
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.word 0x40140000
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PMC:
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.word 0x4007D000
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ACMP0:
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.word 0x40073000
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ACMP1:
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.word 0x40074000
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ADC0:
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.word 0x4003B000
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CLMA:
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.word 0x4007E000
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CLMB:
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.word 0x4007F000
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CRC:
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.word 0x40032000
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DMA:
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.word 0x40080000
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EWM:
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.word 0x4007C000
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/*******************************************************************************
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*
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* Provide weak aliases for each Exception handler to the Default_Handler.
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* As they are weak aliases, any function with the same name will override
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* this definition.
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*
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*******************************************************************************/
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.weak NMI_Handler
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.thumb_set NMI_Handler,Default_Handler
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.weak HardFault_Handler
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.thumb_set HardFault_Handler,Default_Handler
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.weak MemManage_Handler
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.thumb_set MemManage_Handler,Default_Handler
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.weak BusFault_Handler
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.thumb_set BusFault_Handler,Default_Handler
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.weak UsageFault_Handler
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.thumb_set UsageFault_Handler,Default_Handler
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.weak SVC_Handler
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.thumb_set SVC_Handler,Default_Handler
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.weak DebugMon_Handler
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.thumb_set DebugMon_Handler,Default_Handler
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.weak PendSV_Handler
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.thumb_set PendSV_Handler,Default_Handler
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.weak SysTick_Handler
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.thumb_set SysTick_Handler,Default_Handler
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.weak Reserved16_IRQHandler
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.thumb_set Reserved16_IRQHandler,Default_Handler
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.weak Reserved17_IRQHandler
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.thumb_set Reserved17_IRQHandler,Default_Handler
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.weak Reserved18_IRQHandler
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.thumb_set Reserved18_IRQHandler,Default_Handler
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.weak Reserved19_IRQHandler
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.thumb_set Reserved19_IRQHandler,Default_Handler
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.weak Reserved20_IRQHandler
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.thumb_set Reserved20_IRQHandler,Default_Handler
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.weak FMC_IRQHandler
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.thumb_set FMC_IRQHandler,Default_Handler
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.weak PMC_IRQHandler
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.thumb_set PMC_IRQHandler,Default_Handler
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.weak DMA_IRQHandler
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.thumb_set DMA_IRQHandler,Default_Handler
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.weak I2C0_IRQHandler
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.thumb_set I2C0_IRQHandler,Default_Handler
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.weak I2C1_IRQHandler
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.thumb_set I2C1_IRQHandler,Default_Handler
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.weak SPI0_IRQHandler
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.thumb_set SPI0_IRQHandler,Default_Handler
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.weak SPI1_IRQHandler
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.thumb_set SPI1_IRQHandler,Default_Handler
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.weak UART0_IRQHandler
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.thumb_set UART0_IRQHandler,Default_Handler
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.weak UART1_IRQHandler
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.thumb_set UART1_IRQHandler,Default_Handler
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.weak UART2_IRQHandler
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.thumb_set UART2_IRQHandler,Default_Handler
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.weak ADC0_IRQHandler
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.thumb_set ADC0_IRQHandler,Default_Handler
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.weak ACMP0_IRQHandler
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.thumb_set ACMP0_IRQHandler,Default_Handler
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.weak FTM0_IRQHandler
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.thumb_set FTM0_IRQHandler,Default_Handler
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.weak FTM1_IRQHandler
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.thumb_set FTM1_IRQHandler,Default_Handler
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.weak FTM2_IRQHandler
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.thumb_set FTM2_IRQHandler,Default_Handler
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.weak RTC_IRQHandler
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.thumb_set RTC_IRQHandler,Default_Handler
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.weak ACMP1_IRQHandler
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.thumb_set ACMP1_IRQHandler,Default_Handler
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.weak PIT_CH0_IRQHandler
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.thumb_set PIT_CH0_IRQHandler,Default_Handler
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.weak PIT_CH1_IRQHandler
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.thumb_set PIT_CH1_IRQHandler,Default_Handler
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.weak KBI0_IRQHandler
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.thumb_set KBI0_IRQHandler,Default_Handler
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.weak KBI1_IRQHandler
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.thumb_set KBI1_IRQHandler,Default_Handler
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.weak Reserved42_IRQHandler
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.thumb_set Reserved42_IRQHandler,Default_Handler
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.weak ICS_IRQHandler
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.thumb_set ICS_IRQHandler,Default_Handler
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.weak WDOG_IRQHandler
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.thumb_set WDOG_IRQHandler,Default_Handler
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.weak PWT_IRQHandler
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.thumb_set PWT_IRQHandler,Default_Handler
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.weak MCAN_IRQHandler
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.thumb_set MCAN_IRQHandler,Default_Handler
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.weak EXTI0_IRQHandler
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.thumb_set EXTI0_IRQHandler,Default_Handler
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.weak EXTI1_IRQHandler
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.thumb_set EXTI1_IRQHandler,Default_Handler
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.weak EXTI2_IRQHandler
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.thumb_set EXTI2_IRQHandler,Default_Handler
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.weak EXTI3_IRQHandler
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.thumb_set EXTI3_IRQHandler,Default_Handler
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.weak EXTI4_IRQHandler
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.thumb_set EXTI4_IRQHandler,Default_Handler
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.weak EXTI5_IRQHandler
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.thumb_set EXTI5_IRQHandler,Default_Handler
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.weak EXTI6_IRQHandler
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.thumb_set EXTI6_IRQHandler,Default_Handler
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.weak EXTI7_IRQHandler
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.thumb_set EXTI7_IRQHandler,Default_Handler
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.weak EXTI8_IRQHandler
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.thumb_set EXTI8_IRQHandler,Default_Handler
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.weak EXTI9_IRQHandler
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.thumb_set EXTI9_IRQHandler,Default_Handler
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.weak EXTI10_IRQHandler
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.thumb_set EXTI10_IRQHandler,Default_Handler
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.weak EXTI11_IRQHandler
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.thumb_set EXTI11_IRQHandler,Default_Handler
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.weak EXTI12_IRQHandler
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.thumb_set EXTI12_IRQHandler,Default_Handler
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.weak EXTI13_IRQHandler
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.thumb_set EXTI13_IRQHandler,Default_Handler
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.weak EXTI14_IRQHandler
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.thumb_set EXTI14_IRQHandler,Default_Handler
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.weak EXTI15_IRQHandler
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.thumb_set EXTI15_IRQHandler,Default_Handler
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.weak EWM_IRQHandler
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.thumb_set EWM_IRQHandler,Default_Handler
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.weak Reserved21_IRQHandler
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.thumb_set Reserved21_IRQHandler,Default_Handler
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.ifndef RAM_TARGET
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.org 0x400
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/*
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; <h> Flash Configuration
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; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
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; <i> and security information that allows the MCU to restrict acces to the FTFL module.
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; <h> Backdoor Comparison Key
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; <o0> Backdoor Key 0 <0x0-0xFF:2>
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; <o1> Backdoor Key 1 <0x0-0xFF:2>
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; <o2> Backdoor Key 2 <0x0-0xFF:2>
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; <o3> Backdoor Key 3 <0x0-0xFF:2>
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; <o4> Backdoor Key 4 <0x0-0xFF:2>
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; <o5> Backdoor Key 5 <0x0-0xFF:2>
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; <o6> Backdoor Key 6 <0x0-0xFF:2>
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; <o7> Backdoor Key 7 <0x0-0xFF:2>
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*/
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.set BackDoorK0, 0xff
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.set BackDoorK1, 0xff
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.set BackDoorK2, 0xff
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.set BackDoorK3, 0xff
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.set BackDoorK4, 0xff
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.set BackDoorK5, 0xff
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.set BackDoorK6, 0xff
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.set BackDoorK7, 0xff
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/*
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; </h>
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; <h> FPROT
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; <i> P-Flash Protection Register
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; <o.7> FPOPEN
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; <0=> FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS and FPLS bits FPROT1.1
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; <1=> FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS and FPLS bits
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; <o.5> FPHDIS
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; <0=> Protection/Unprotection enabled
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; <1=> Protection/Unprotection disabled
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; <o.3..4> FPHS
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; <0=> Address range: 0x00_7C00-0x00_7FFF; protected size: 1 KB
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; <1=> Address range: 0x00_7800-0x00_7FFF; protected size: 2 KB
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; <2=> Address range: 0x00_7000-0x00_7FFF; protected size: 4 KB
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; <3=> Address range: 0x00_6000-0x00_7FFF; protected size: 8 KB
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; <o.5> FPLDIS
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; <0=> Protection/Unprotection enabled
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; <1=> Protection/Unprotection disabled
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; <o.3..4> FPLS
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; <0=> Address range: 0x00_0000-0x00_07FF; protected size: 2 KB
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; <1=> Address range: 0x00_0000-0x00_0FFF; protected size: 4 KB
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; <2=> Address range: 0x00_0000-0x00_1FFF; protected size: 8 KB
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; <3=> Address range: 0x00_0000-0x00_3FFF; protected size: 16 KB
|
*/
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.set FPROT, 0xff
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/*
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; </h>
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; </h>
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; <h> Flash security byte (FSEC)
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; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
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; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
|
; <o.0..1> SEC
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; <2=> MCU security status is unsecure
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; <3=> MCU security status is secure
|
; <i> Flash Security
|
; <i> This bits define the security state of the MCU.
|
; <o.6..7> KEYEN
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; <2=> Backdoor key access enabled
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; <3=> Backdoor key access disabled
|
; <i> Backdoor key Security Enable
|
; <i> These bits enable and disable backdoor key access to the FTFL module.
|
*/
|
.set FSEC, 0xff
|
/*
|
; </h>
|
; <h> Flash Option Register (FOPT)
|
*/
|
.set FOPT, 0xff
|
|
.byte BackDoorK0
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.byte BackDoorK1
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.byte BackDoorK2
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.byte BackDoorK3
|
.byte BackDoorK4
|
.byte BackDoorK5
|
.byte BackDoorK6
|
.byte BackDoorK7
|
.byte 0xff
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.byte 0xff
|
.byte 0xff
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.byte 0xff
|
.byte 0xff
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.byte FPROT
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.byte FSEC
|
.byte FOPT
|
.endif
|
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/******************* (C) COPYRIGHT 2011 CHIPWAYS *****END OF FILE****/
|
