/**
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******************************************************************************
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* @file xl_port.h
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* @author software group
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* @brief This file contains all the functions prototypes for the PORT
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* firmware library.
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******************************************************************************
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* @attention
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*
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* 2019 by Chipways Communications,Inc. All Rights Reserved.
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* This software is supplied under the terms of a license
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* agreement or non-disclosure agreement with Chipways.
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* Passing on and copying of this document,and communication
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* of its contents is not permitted without prior written
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* authorization.
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*
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* <h2><center>© COPYRIGHT 2019 Chipways</center></h2>
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef XL_PORT_H
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#define XL_PORT_H
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#ifdef __cplusplus
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extern "C"{
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#endif
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/* Includes ---------------------------------------------------------------*/
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#include "XL6600.h"
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/* Register define ------------------------------------------------------------*/
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/* IOFLT0 Bit Fields */
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#define PORT_IOFLT0_FLTA_MASK 0x3u
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#define PORT_IOFLT0_FLTA_SHIFT 0
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#define PORT_IOFLT0_FLTB_MASK 0xCu
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#define PORT_IOFLT0_FLTB_SHIFT 2
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#define PORT_IOFLT0_FLTC_MASK 0x30u
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#define PORT_IOFLT0_FLTC_SHIFT 4
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#define PORT_IOFLT0_FLTD_MASK 0xC0u
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#define PORT_IOFLT0_FLTD_SHIFT 6
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#define PORT_IOFLT0_FLTE_MASK 0x300u
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#define PORT_IOFLT0_FLTE_SHIFT 8
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#define PORT_IOFLT0_FLTF_MASK 0xC00u
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#define PORT_IOFLT0_FLTF_SHIFT 10
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#define PORT_IOFLT0_FLTG_MASK 0x3000u
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#define PORT_IOFLT0_FLTG_SHIFT 12
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#define PORT_IOFLT0_FLTH_MASK 0xC000u
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#define PORT_IOFLT0_FLTH_SHIFT 14
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#define PORT_IOFLT0_FLTRST_MASK 0x30000u
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#define PORT_IOFLT0_FLTRST_SHIFT 16
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#define PORT_IOFLT0_FLTKBI0_MASK 0xC0000u
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#define PORT_IOFLT0_FLTKBI0_SHIFT 18
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#define PORT_IOFLT0_FLTKBI1_MASK 0x300000u
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#define PORT_IOFLT0_FLTKBI1_SHIFT 20
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#define PORT_IOFLT0_FLTNMI_MASK 0xC00000u
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#define PORT_IOFLT0_FLTNMI_SHIFT 22
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#define PORT_IOFLT0_FLTDIV1_MASK 0x3000000u
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#define PORT_IOFLT0_FLTDIV1_SHIFT 24
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#define PORT_IOFLT0_FLTDIV2_MASK 0x1C000000u
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#define PORT_IOFLT0_FLTDIV2_SHIFT 26
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#define PORT_IOFLT0_FLTDIV3_MASK 0xE0000000u
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#define PORT_IOFLT0_FLTDIV3_SHIFT 29
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/* IOFLT1 Bit Fields */
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#define PORT_IOFLT1_FLTI_MASK 0x3u
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#define PORT_IOFLT1_FLTI_SHIFT 0
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#define PORT_IOFLT1_FLTIRQ_MASK 0x30u
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#define PORT_IOFLT1_FLTIRQ_SHIFT 4
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#define PORT_IOFLT1_FLTFTM0_MASK 0xC0u
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#define PORT_IOFLT1_FLTFTM0_SHIFT 6
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#define PORT_IOFLT1_FLTFTM1_MASK 0x300u
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#define PORT_IOFLT1_FLTFTM1_SHIFT 8
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#define PORT_IOFLT1_FLTPWT_MASK 0xC00u
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#define PORT_IOFLT1_FLTPWT_SHIFT 10
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#define PORT_IOFLT1_FLTI2C0_MASK 0x3000u
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#define PORT_IOFLT1_FLTI2C0_SHIFT 12
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#define PORT_IOFLT1_FLTI2C1_MASK 0xC000u
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#define PORT_IOFLT1_FLTI2C1_SHIFT 14
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#define PORT_IOFLT1_FLTEWM_MASK 0x30000u
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#define PORT_IOFLT1_FLTEWM_SHIFT 16
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/* PUE0 Bit Fields */
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#define PORT_PUE0_PTAPE0_MASK 0x1u
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#define PORT_PUE0_PTAPE0_SHIFT 0
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#define PORT_PUE0_PTAPE1_MASK 0x2u
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#define PORT_PUE0_PTAPE1_SHIFT 1
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#define PORT_PUE0_PTAPE2_MASK 0x4u
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#define PORT_PUE0_PTAPE2_SHIFT 2
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#define PORT_PUE0_PTAPE3_MASK 0x8u
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#define PORT_PUE0_PTAPE3_SHIFT 3
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#define PORT_PUE0_PTAPE4_MASK 0x10u
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#define PORT_PUE0_PTAPE4_SHIFT 4
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#define PORT_PUE0_PTAPE5_MASK 0x20u
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#define PORT_PUE0_PTAPE5_SHIFT 5
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#define PORT_PUE0_PTAPE6_MASK 0x40u
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#define PORT_PUE0_PTAPE6_SHIFT 6
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#define PORT_PUE0_PTAPE7_MASK 0x80u
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#define PORT_PUE0_PTAPE7_SHIFT 7
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#define PORT_PUE0_PTBPE0_MASK 0x100u
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#define PORT_PUE0_PTBPE0_SHIFT 8
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#define PORT_PUE0_PTBPE1_MASK 0x200u
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#define PORT_PUE0_PTBPE1_SHIFT 9
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#define PORT_PUE0_PTBPE2_MASK 0x400u
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#define PORT_PUE0_PTBPE2_SHIFT 10
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#define PORT_PUE0_PTBPE3_MASK 0x800u
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#define PORT_PUE0_PTBPE3_SHIFT 11
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#define PORT_PUE0_PTBPE4_MASK 0x1000u
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#define PORT_PUE0_PTBPE4_SHIFT 12
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#define PORT_PUE0_PTBPE5_MASK 0x2000u
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#define PORT_PUE0_PTBPE5_SHIFT 13
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#define PORT_PUE0_PTBPE6_MASK 0x4000u
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#define PORT_PUE0_PTBPE6_SHIFT 14
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#define PORT_PUE0_PTBPE7_MASK 0x8000u
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#define PORT_PUE0_PTBPE7_SHIFT 15
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#define PORT_PUE0_PTCPE0_MASK 0x10000u
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#define PORT_PUE0_PTCPE0_SHIFT 16
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#define PORT_PUE0_PTCPE1_MASK 0x20000u
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#define PORT_PUE0_PTCPE1_SHIFT 17
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#define PORT_PUE0_PTCPE2_MASK 0x40000u
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#define PORT_PUE0_PTCPE2_SHIFT 18
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#define PORT_PUE0_PTCPE3_MASK 0x80000u
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#define PORT_PUE0_PTCPE3_SHIFT 19
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#define PORT_PUE0_PTCPE4_MASK 0x100000u
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#define PORT_PUE0_PTCPE4_SHIFT 20
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#define PORT_PUE0_PTCPE5_MASK 0x200000u
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#define PORT_PUE0_PTCPE5_SHIFT 21
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#define PORT_PUE0_PTCPE6_MASK 0x400000u
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#define PORT_PUE0_PTCPE6_SHIFT 22
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#define PORT_PUE0_PTCPE7_MASK 0x800000u
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#define PORT_PUE0_PTCPE7_SHIFT 23
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#define PORT_PUE0_PTDPE0_MASK 0x1000000u
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#define PORT_PUE0_PTDPE0_SHIFT 24
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#define PORT_PUE0_PTDPE1_MASK 0x2000000u
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#define PORT_PUE0_PTDPE1_SHIFT 25
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#define PORT_PUE0_PTDPE2_MASK 0x4000000u
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#define PORT_PUE0_PTDPE2_SHIFT 26
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#define PORT_PUE0_PTDPE3_MASK 0x8000000u
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#define PORT_PUE0_PTDPE3_SHIFT 27
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#define PORT_PUE0_PTDPE4_MASK 0x10000000u
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#define PORT_PUE0_PTDPE4_SHIFT 28
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#define PORT_PUE0_PTDPE5_MASK 0x20000000u
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#define PORT_PUE0_PTDPE5_SHIFT 29
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#define PORT_PUE0_PTDPE6_MASK 0x40000000u
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#define PORT_PUE0_PTDPE6_SHIFT 30
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#define PORT_PUE0_PTDPE7_MASK 0x80000000u
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#define PORT_PUE0_PTDPE7_SHIFT 31
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/* PUE1 Bit Fields */
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#define PORT_PUE1_PTEPE0_MASK 0x1u
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#define PORT_PUE1_PTEPE0_SHIFT 0
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#define PORT_PUE1_PTEPE1_MASK 0x2u
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#define PORT_PUE1_PTEPE1_SHIFT 1
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#define PORT_PUE1_PTEPE2_MASK 0x4u
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#define PORT_PUE1_PTEPE2_SHIFT 2
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#define PORT_PUE1_PTEPE3_MASK 0x8u
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#define PORT_PUE1_PTEPE3_SHIFT 3
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#define PORT_PUE1_PTEPE4_MASK 0x10u
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#define PORT_PUE1_PTEPE4_SHIFT 4
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#define PORT_PUE1_PTEPE5_MASK 0x20u
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#define PORT_PUE1_PTEPE5_SHIFT 5
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#define PORT_PUE1_PTEPE6_MASK 0x40u
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#define PORT_PUE1_PTEPE6_SHIFT 6
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#define PORT_PUE1_PTEPE7_MASK 0x80u
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#define PORT_PUE1_PTEPE7_SHIFT 7
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#define PORT_PUE1_PTFPE0_MASK 0x100u
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#define PORT_PUE1_PTFPE0_SHIFT 8
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#define PORT_PUE1_PTFPE1_MASK 0x200u
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#define PORT_PUE1_PTFPE1_SHIFT 9
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#define PORT_PUE1_PTFPE2_MASK 0x400u
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#define PORT_PUE1_PTFPE2_SHIFT 10
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#define PORT_PUE1_PTFPE3_MASK 0x800u
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#define PORT_PUE1_PTFPE3_SHIFT 11
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#define PORT_PUE1_PTFPE4_MASK 0x1000u
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#define PORT_PUE1_PTFPE4_SHIFT 12
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#define PORT_PUE1_PTFPE5_MASK 0x2000u
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#define PORT_PUE1_PTFPE5_SHIFT 13
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#define PORT_PUE1_PTFPE6_MASK 0x4000u
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#define PORT_PUE1_PTFPE6_SHIFT 14
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#define PORT_PUE1_PTFPE7_MASK 0x8000u
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#define PORT_PUE1_PTFPE7_SHIFT 15
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#define PORT_PUE1_PTGPE0_MASK 0x10000u
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#define PORT_PUE1_PTGPE0_SHIFT 16
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#define PORT_PUE1_PTGPE1_MASK 0x20000u
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#define PORT_PUE1_PTGPE1_SHIFT 17
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#define PORT_PUE1_PTGPE2_MASK 0x40000u
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#define PORT_PUE1_PTGPE2_SHIFT 18
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#define PORT_PUE1_PTGPE3_MASK 0x80000u
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#define PORT_PUE1_PTGPE3_SHIFT 19
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#define PORT_PUE1_PTGPE4_MASK 0x100000u
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#define PORT_PUE1_PTGPE4_SHIFT 20
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#define PORT_PUE1_PTGPE5_MASK 0x200000u
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#define PORT_PUE1_PTGPE5_SHIFT 21
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#define PORT_PUE1_PTGPE6_MASK 0x400000u
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#define PORT_PUE1_PTGPE6_SHIFT 22
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#define PORT_PUE1_PTGPE7_MASK 0x800000u
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#define PORT_PUE1_PTGPE7_SHIFT 23
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#define PORT_PUE1_PTHPE0_MASK 0x1000000u
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#define PORT_PUE1_PTHPE0_SHIFT 24
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#define PORT_PUE1_PTHPE1_MASK 0x2000000u
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#define PORT_PUE1_PTHPE1_SHIFT 25
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#define PORT_PUE1_PTHPE2_MASK 0x4000000u
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#define PORT_PUE1_PTHPE2_SHIFT 26
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#define PORT_PUE1_PTHPE3_MASK 0x8000000u
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#define PORT_PUE1_PTHPE3_SHIFT 27
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#define PORT_PUE1_PTHPE4_MASK 0x10000000u
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#define PORT_PUE1_PTHPE4_SHIFT 28
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#define PORT_PUE1_PTHPE5_MASK 0x20000000u
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#define PORT_PUE1_PTHPE5_SHIFT 29
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#define PORT_PUE1_PTHPE6_MASK 0x40000000u
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#define PORT_PUE1_PTHPE6_SHIFT 30
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#define PORT_PUE1_PTHPE7_MASK 0x80000000u
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#define PORT_PUE1_PTHPE7_SHIFT 31
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/* PUE2 Bit Fields */
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#define PORT_PUE2_PTIPE0_MASK 0x1u
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#define PORT_PUE2_PTIPE0_SHIFT 0
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#define PORT_PUE2_PTIPE1_MASK 0x2u
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#define PORT_PUE2_PTIPE1_SHIFT 1
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#define PORT_PUE2_PTIPE2_MASK 0x4u
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#define PORT_PUE2_PTIPE2_SHIFT 2
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#define PORT_PUE2_PTIPE3_MASK 0x8u
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#define PORT_PUE2_PTIPE3_SHIFT 3
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#define PORT_PUE2_PTIPE4_MASK 0x10u
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#define PORT_PUE2_PTIPE4_SHIFT 4
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#define PORT_PUE2_PTIPE5_MASK 0x20u
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#define PORT_PUE2_PTIPE5_SHIFT 5
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#define PORT_PUE2_PTIPE6_MASK 0x40u
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#define PORT_PUE2_PTIPE6_SHIFT 6
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/* HDRVE Bit Fields */
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#define PORT_HDRVE_PTB4_MASK 0x1u
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#define PORT_HDRVE_PTB4_SHIFT 0
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#define PORT_HDRVE_PTB5_MASK 0x2u
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#define PORT_HDRVE_PTB5_SHIFT 1
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#define PORT_HDRVE_PTD0_MASK 0x4u
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#define PORT_HDRVE_PTD0_SHIFT 2
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#define PORT_HDRVE_PTD1_MASK 0x8u
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#define PORT_HDRVE_PTD1_SHIFT 3
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#define PORT_HDRVE_PTE0_MASK 0x10u
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#define PORT_HDRVE_PTE0_SHIFT 4
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#define PORT_HDRVE_PTE1_MASK 0x20u
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#define PORT_HDRVE_PTE1_SHIFT 5
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#define PORT_HDRVE_PTH0_MASK 0x40u
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#define PORT_HDRVE_PTH0_SHIFT 6
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#define PORT_HDRVE_PTH1_MASK 0x80u
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#define PORT_HDRVE_PTH1_SHIFT 7
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/** PORT - Register Layout Typedef */
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typedef struct {
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__IO uint32_t IOFLT0; /*!< ¶Ë¿ÚÂ˲¨¼Ä´æÆ÷0, offset: 0x0 */
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__IO uint32_t IOFLT1; /*!< ¶Ë¿ÚÂ˲¨¼Ä´æÆ÷1, offset: 0x4 */
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__IO uint32_t PUE0; /*!< ¶Ë¿ÚÉÏÀʹÄܼĴæÆ÷0, offset: 0x8 */
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__IO uint32_t PUE1; /*!< ¶Ë¿ÚÉÏÀʹÄܼĴæÆ÷1, offset: 0xC */
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__IO uint32_t PUE2; /*!< ¶Ë¿ÚÉÏÀʹÄܼĴæÆ÷2, offset: 0x10 */
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__IO uint32_t HDRVE; /*!< ¶Ë¿Ú´óµçÁ÷Çý¶¯Ê¹ÄܼĴæÆ÷, offset: 0x14 */
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} PORT_Type, *PORT_MemMapPtr;
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extern PORT_Type* PORT;
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/** @addtogroup XL6600_StdPeriph_Driver
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* @{
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*/
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/** @addtogroup PORT
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/**
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* @brief PORT¶Ë¿ÚÂ˲¨Æ÷0½á¹¹Ì嶨Òå
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*/
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typedef struct
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{
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uint32_t iofltdiv3; /*!< ¶Ë¿ÚÂ˲¨Æ÷·Ö×é 3 */
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uint32_t iofltdiv2; /*!< ¶Ë¿ÚÂ˲¨Æ÷·Ö×é 2 */
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uint32_t iofltdiv1; /*!< ¶Ë¿ÚÂ˲¨Æ÷·Ö×é 1 */
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uint32_t iofltnmi; /*!< Õë¶Ô NMI ÊäÈëµÄÂ˲¨Æ÷Ñ¡Ôñ */
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uint32_t iofltkbi1; /*!< Õë¶Ô KBI1 ÊäÈëµÄÂ˲¨Æ÷Ñ¡Ôñ */
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uint32_t iofltkbi0; /*!< Õë¶Ô KBI0 ÊäÈëµÄÂ˲¨Æ÷Ñ¡Ôñ */
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uint32_t iofltrst; /*!< Õë¶Ô RESET ÊäÈëµÄÂ˲¨Æ÷Ñ¡Ôñ */
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uint32_t iofltpth; /*!< Õë¶Ô PTH ÊäÈëµÄÂ˲¨Æ÷Ñ¡Ôñ */
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uint32_t iofltptg; /*!< Õë¶Ô PTG ÊäÈëµÄÂ˲¨Æ÷Ñ¡Ôñ */
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uint32_t iofltptf; /*!< Õë¶Ô PTF ÊäÈëµÄÂ˲¨Æ÷Ñ¡Ôñ */
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uint32_t iofltpte; /*!< Õë¶Ô PTE ÊäÈëµÄÂ˲¨Æ÷Ñ¡Ôñ */
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uint32_t iofltptd; /*!< Õë¶Ô PTD ÊäÈëµÄÂ˲¨Æ÷Ñ¡Ôñ */
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uint32_t iofltptc; /*!< Õë¶Ô PTC ÊäÈëµÄÂ˲¨Æ÷Ñ¡Ôñ */
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uint32_t iofltptb; /*!< Õë¶Ô PTB ÊäÈëµÄÂ˲¨Æ÷Ñ¡Ôñ */
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uint32_t iofltpta; /*!< Õë¶Ô PTA ÊäÈëµÄÂ˲¨Æ÷Ñ¡Ôñ */
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}port_ioflt0_config;
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/**
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* @brief PORT¶Ë¿ÚÂ˲¨Æ÷1½á¹¹Ì嶨Òå
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*/
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typedef struct
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{
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uint16_t ioflti2c1; /*!< Õë¶Ô SCL1/SDA1 ÊäÈëµÄÂ˲¨Æ÷Ñ¡Ôñ */
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uint16_t ioflti2c0; /*!< Õë¶Ô SCL0/SDA0 ÊäÈëµÄÂ˲¨Æ÷Ñ¡Ôñ */
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uint16_t iofltpwt; /*!< Õë¶Ô PWT_IN1/PWT_IN0 ÊäÈëµÄÂ˲¨Æ÷Ñ¡Ôñ */
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uint16_t iofltftm1; /*!< Õë¶Ô FTM1CH0/FTM1CH1 ÊäÈëµÄÂ˲¨Æ÷Ñ¡Ôñ */
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uint16_t iofltftm0; /*!< Õë¶Ô FTM0CH0/FTM0CH1 ÊäÈëµÄÂ˲¨Æ÷Ñ¡Ôñ */
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uint16_t iofltirq; /*!< Õë¶Ô IRQ ÊäÈëµÄÂ˲¨Æ÷Ñ¡Ôñ */
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uint16_t iofltpti; /*!< Õë¶Ô PTI ÊäÈëµÄÂ˲¨Æ÷Ñ¡Ôñ */
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}port_ioflt1_config;
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup PORT_Exported_Constants PORTÄ£¿éʹÓòÎÊý¶¨Òå
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* @{
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*/
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/** @defgroup PORT_Filter_Division_3 PORTÂ˲¨Æ÷·Ö×é3ÉèÖö¨Òå
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* @{
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*/
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#define Port_FLTDIV3SetLPOCLK ((uint32_t)0x00000000u) /*!< LPOCLK */
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#define Port_FLTDIV3SetLPOCLKDiv2 ((uint32_t)0x20000000u) /*!< LPOCLK/2 */
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#define Port_FLTDIV3SetLPOCLKDiv4 ((uint32_t)0x40000000u) /*!< LPOCLK/4 */
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#define Port_FLTDIV3SetLPOCLKDiv8 ((uint32_t)0x60000000u) /*!< LPOCLK/8 */
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#define Port_FLTDIV3SetLPOCLKDiv16 ((uint32_t)0x80000000u) /*!< LPOCLK/16 */
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#define Port_FLTDIV3SetLPOCLKDiv32 ((uint32_t)0xA0000000u) /*!< LPOCLK/32 */
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#define Port_FLTDIV3SetLPOCLKDiv64 ((uint32_t)0xC0000000u) /*!< LPOCLK/64 */
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#define Port_FLTDIV3SetLPOCLKDiv128 ((uint32_t)0xE0000000u) /*!< LPOCLK/128 */
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/**
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* @}
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*/
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/** @defgroup PORT_Filter_Division_2 PORTÂ˲¨Æ÷·Ö×é2ÉèÖö¨Òå
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* @{
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*/
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#define Port_FLTDIV2SetBUSCLKDiv32 ((uint32_t)0x00000000u) /*!< BUSCLK/32 */
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#define Port_FLTDIV2SetBUSCLKDiv64 ((uint32_t)0x04000000u) /*!< BUSCLK/64 */
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#define Port_FLTDIV2SetBUSCLKDiv128 ((uint32_t)0x08000000u) /*!< BUSCLK/128 */
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#define Port_FLTDIV2SetBUSCLKDiv256 ((uint32_t)0x0C000000u) /*!< BUSCLK/256 */
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#define Port_FLTDIV2SetBUSCLKDiv512 ((uint32_t)0x10000000u) /*!< BUSCLK/512 */
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#define Port_FLTDIV2SetBUSCLKDiv1024 ((uint32_t)0x14000000u) /*!< BUSCLK/1024 */
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#define Port_FLTDIV2SetBUSCLKDiv2048 ((uint32_t)0x18000000u) /*!< BUSCLK/2048 */
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#define Port_FLTDIV2SetBUSCLKDiv4096 ((uint32_t)0x1C000000u) /*!< BUSCLK/4096 */
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/**
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* @}
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*/
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/** @defgroup PORT_Filter_Division_1 PORTÂ˲¨Æ÷·Ö×é1ÉèÖö¨Òå
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* @{
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*/
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#define Port_FLTDIV1SetBUSCLKDiv2 ((uint32_t)0x00000000) /*!< BUSCLK/2 */
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#define Port_FLTDIV1SetBUSCLKDiv4 ((uint32_t)0x01000000) /*!< BUSCLK/4 */
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#define Port_FLTDIV1SetBUSCLKDiv8 ((uint32_t)0x02000000) /*!< BUSCLK/8 */
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#define Port_FLTDIV1SetBUSCLKDiv16 ((uint32_t)0x03000000) /*!< BUSCLK/16 */
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/**
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* @}
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*/
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/** @defgroup PORT_NMI_Filter_Division_Seclect PORTÕë¶ÔNMIÊäÈëÂ˲¨Ñ¡Ôñ¶¨Òå
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* @{
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*/
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#define Port_FLTNMINoFilter ((uint32_t)0x00000000) /*!< ÎÞÂ˲¨Æ÷ */
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#define Port_FLTNMIFLTDIV1 ((uint32_t)0x00400000) /*!< Selects FLTDIV1, Stop ģʽÏÂ×Ô¶¯Çл»µ½FLTDIV3 */
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#define Port_FLTNMIFLTDIV2 ((uint32_t)0x00800000) /*!< Selects FLTDIV2, Stop ģʽÏÂ×Ô¶¯Çл»µ½FLTDIV3 */
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#define Port_FLTNMIFLTDIV3 ((uint32_t)0x00C00000) /*!< FLTDIV3 */
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/**
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* @}
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*/
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/** @defgroup PORT_KBI1_Filter_Division_Seclect PORTÕë¶ÔKBI1ÊäÈëÂ˲¨Ñ¡Ôñ¶¨Òå
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* @{
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*/
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#define Port_FLTKBI1NoFilter ((uint32_t)0x00000000) /*!< ÎÞÂ˲¨Æ÷ */
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#define Port_FLTKBI1FLTDIV1 ((uint32_t)0x00100000) /*!< Selects FLTDIV1, Stop ģʽÏÂ×Ô¶¯Çл»µ½FLTDIV3 */
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#define Port_FLTKBI1FLTDIV2 ((uint32_t)0x00200000) /*!< Selects FLTDIV2, Stop ģʽÏÂ×Ô¶¯Çл»µ½FLTDIV3 */
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#define Port_FLTKBI1FLTDIV3 ((uint32_t)0x00300000) /*!< FLTDIV3 */
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/**
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* @}
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*/
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/** @defgroup PORT_KBI0_Filter_Division_Seclect PORTÕë¶ÔKBI0ÊäÈëÂ˲¨Ñ¡Ôñ¶¨Òå
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* @{
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*/
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#define Port_FLTKBI0NoFilter ((uint32_t)0x00000000) /*!< ÎÞÂ˲¨Æ÷ */
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#define Port_FLTKBI0FLTDIV1 ((uint32_t)0x00040000) /*!< Selects FLTDIV1, Stop ģʽÏÂ×Ô¶¯Çл»µ½FLTDIV3 */
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#define Port_FLTKBI0FLTDIV2 ((uint32_t)0x00080000) /*!< Selects FLTDIV2, Stop ģʽÏÂ×Ô¶¯Çл»µ½FLTDIV3 */
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#define Port_FLTKBI0FLTDIV3 ((uint32_t)0x000C0000) /*!< FLTDIV3 */
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/**
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* @}
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*/
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/** @defgroup PORT_RESET/IRQ_Filter_Division_Seclect PORTÕë¶ÔRESET/IRQÊäÈëÂ˲¨Ñ¡Ôñ¶¨Òå
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* @{
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*/
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#define Port_FLTRSTNoFilter ((uint32_t)0x00000000) /*!< ÎÞÂ˲¨Æ÷ */
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#define Port_FLTRSTFLTDIV1 ((uint32_t)0x00010000) /*!< Selects FLTDIV1, Stop ģʽÏÂ×Ô¶¯Çл»µ½FLTDIV3 */
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#define Port_FLTRSTFLTDIV2 ((uint32_t)0x00020000) /*!< Selects FLTDIV2, Stop ģʽÏÂ×Ô¶¯Çл»µ½FLTDIV3 */
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#define Port_FLTRSTFLTDIV3 ((uint32_t)0x00030000) /*!< FLTDIV3 */
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/**
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* @}
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*/
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/** @defgroup PORT_PTH_Filter_Division_Seclect PORTÕë¶ÔPTHÊäÈëÂ˲¨Ñ¡Ôñ¶¨Òå
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* @{
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*/
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#define Port_FLTHBUSCLK ((uint32_t)0x00000000) /*!< BUSCLK */
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#define Port_FLTHFLTDIV1 ((uint32_t)0x00004000) /*!< BUSCLK1 */
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#define Port_FLTHFLTDIV2 ((uint32_t)0x00008000) /*!< BUSCLK2 */
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#define Port_FLTHFLTDIV3 ((uint32_t)0x0000C000) /*!< BUSCLK3 */
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/**
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* @}
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*/
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/** @defgroup PORT_PTG_Filter_Division_Seclect PORTÕë¶ÔPTGÊäÈëÂ˲¨Ñ¡Ôñ¶¨Òå
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* @{
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*/
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#define Port_FLTGBUSCLK ((uint32_t)0x00000000) /*!< BUSCLK */
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#define Port_FLTGFLTDIV1 ((uint32_t)0x00001000) /*!< FLTDIV1 */
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#define Port_FLTGFLTDIV2 ((uint32_t)0x00002000) /*!< FLTDIV2 */
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#define Port_FLTGFLTDIV3 ((uint32_t)0x00003000) /*!< FLTDIV3 */
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/**
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* @}
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*/
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/** @defgroup PORT_PTF_Filter_Division_Seclect PORTÕë¶ÔPTFÊäÈëÂ˲¨Ñ¡Ôñ¶¨Òå
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* @{
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*/
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#define Port_FLTFBUSCLK ((uint32_t)0x00000000) /*!< BUSCLK */
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#define Port_FLTFFLTDIV1 ((uint32_t)0x00000400) /*!< FLTDIV1 */
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#define Port_FLTFFLTDIV2 ((uint32_t)0x00000800) /*!< FLTDIV2 */
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#define Port_FLTFFLTDIV3 ((uint32_t)0x00000C00) /*!< FLTDIV3 */
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/**
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* @}
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*/
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/** @defgroup PORT_PTE_Filter_Division_Seclect PORTÕë¶ÔPTEÊäÈëÂ˲¨Ñ¡Ôñ¶¨Òå
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* @{
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*/
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#define Port_FLTEBUSCLK ((uint32_t)0x00000000) /*!< BUSCLK */
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#define Port_FLTEFLTDIV1 ((uint32_t)0x00000100) /*!< FLTDIV1 */
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#define Port_FLTEFLTDIV2 ((uint32_t)0x00000200) /*!< FLTDIV2 */
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#define Port_FLTEFLTDIV3 ((uint32_t)0x00000300) /*!< FLTDIV3 */
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/**
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* @}
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*/
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/** @defgroup PORT_PTD_Filter_Division_Seclect PORTÕë¶ÔPTDÊäÈëÂ˲¨Ñ¡Ôñ¶¨Òå
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* @{
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*/
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#define Port_FLTDBUSCLK ((uint32_t)0x00000000) /*!< BUSCLK */
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#define Port_FLTDFLTDIV1 ((uint32_t)0x00000040) /*!< FLTDIV1 */
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#define Port_FLTDFLTDIV2 ((uint32_t)0x00000080) /*!< FLTDIV2 */
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#define Port_FLTDFLTDIV3 ((uint32_t)0x000000C0) /*!< FLTDIV3 */
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/**
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* @}
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*/
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/** @defgroup PORT_PTC_Filter_Division_Seclect PORTÕë¶ÔPTCÊäÈëÂ˲¨Ñ¡Ôñ¶¨Òå
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* @{
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*/
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#define Port_FLTCBUSCLK ((uint32_t)0x00000000) /*!< BUSCLK */
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#define Port_FLTCFLTDIV1 ((uint32_t)0x00000010) /*!< FLTDIV1 */
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#define Port_FLTCFLTDIV2 ((uint32_t)0x00000020) /*!< FLTDIV2 */
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#define Port_FLTCFLTDIV3 ((uint32_t)0x00000030) /*!< FLTDIV3 */
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/**
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* @}
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*/
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/** @defgroup PORT_PTB_Filter_Division_Seclect PORTÕë¶ÔPTBÊäÈëÂ˲¨Ñ¡Ôñ¶¨Òå
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* @{
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*/
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#define Port_FLTBBUSCLK ((uint32_t)0x00000000) /*!< BUSCLK */
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#define Port_FLTBFLTDIV1 ((uint32_t)0x00000004) /*!< FLTDIV1 */
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#define Port_FLTBFLTDIV2 ((uint32_t)0x00000008) /*!< FLTDIV2 */
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#define Port_FLTBFLTDIV3 ((uint32_t)0x0000000C) /*!< FLTDIV3 */
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/**
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* @}
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*/
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/** @defgroup PORT_PTA_Filter_Division_Seclect PORTÕë¶ÔPTAÊäÈëÂ˲¨Ñ¡Ôñ¶¨Òå
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* @{
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*/
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#define Port_FLTABUSCLK ((uint32_t)0x00000000) /*!< BUSCLK */
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#define Port_FLTAFLTDIV1 ((uint32_t)0x00000001) /*!< FLTDIV1 */
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#define Port_FLTAFLTDIV2 ((uint32_t)0x00000002) /*!< FLTDIV2 */
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#define Port_FLTAFLTDIV3 ((uint32_t)0x00000003) /*!< FLTDIV3 */
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/**
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* @}
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*/
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/** @defgroup PORT_EWM_Filter_Division_Seclect PORTÕë¶ÔEWMÊäÈëÂ˲¨Ñ¡Ôñ¶¨Òå
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* @{
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*/
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#define Port_FLTEWMNoFilter ((uint16_t)0x00000) /*!< ÎÞÂ˲¨Æ÷ */
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#define Port_FLTEWMFLTDIV1 ((uint16_t)0x10000) /*!< FLTDIV1 */
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#define Port_FLTEWMFLTDIV2 ((uint16_t)0x20000) /*!< FLTDIV2 */
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#define Port_FLTIEWMBUSCLK ((uint16_t)0x30000) /*!< FLTDIV3 */
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/**
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* @}
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*/
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/** @defgroup PORT_I2C1_Filter_Division_Seclect PORTÕë¶ÔI2C1ÊäÈëÂ˲¨Ñ¡Ôñ¶¨Òå
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* @{
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*/
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#define Port_FLTI2C1NoFilter ((uint16_t)0x0000) /*!< ÎÞÂ˲¨Æ÷ */
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#define Port_FLTI2C1FLTDIV1 ((uint16_t)0x4000) /*!< FLTDIV1 */
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#define Port_FLTI2C1FLTDIV2 ((uint16_t)0x8000) /*!< FLTDIV2 */
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#define Port_FLTI2C1BUSCLK ((uint16_t)0xC000) /*!< FLTDIV3 */
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/**
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* @}
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*/
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/** @defgroup PORT_I2C0_Filter_Division_Seclect PORTÕë¶ÔI2C0ÊäÈëÂ˲¨Ñ¡Ôñ¶¨Òå
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* @{
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*/
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#define Port_FLTI2C0NoFilter ((uint16_t)0x0000) /*!< ÎÞÂ˲¨Æ÷ */
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#define Port_FLTI2C0FLTDIV1 ((uint16_t)0x1000) /*!< FLTDIV1 */
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#define Port_FLTI2C0FLTDIV2 ((uint16_t)0x2000) /*!< FLTDIV2 */
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#define Port_FLTI2C0BUSCLK ((uint16_t)0x3000) /*!< FLTDIV3 */
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/**
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* @}
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*/
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/** @defgroup PORT_PWT_Filter_Division_Seclect PORTÕë¶ÔPWTÊäÈëÂ˲¨Ñ¡Ôñ¶¨Òå
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* @{
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*/
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#define Port_FLTPWTNoFilter ((uint16_t)0x0000) /*!< ÎÞÂ˲¨Æ÷ */
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#define Port_FLTPWTFLTDIV1 ((uint16_t)0x0400) /*!< FLTDIV1 */
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#define Port_FLTPWTFLTDIV2 ((uint16_t)0x0800) /*!< FLTDIV2 */
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#define Port_FLTPWTFLTDIV3 ((uint16_t)0x0C00) /*!< FLTDIV3 */
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/**
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* @}
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*/
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/** @defgroup PORT_FTM1_Filter_Division_Seclect PORTÕë¶ÔFTM1ÊäÈëÂ˲¨Ñ¡Ôñ¶¨Òå
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* @{
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*/
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#define Port_FLTFTM1NoFilter ((uint16_t)0x0000) /*!< No filter */
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#define Port_FLTFTM1FLTDIV1 ((uint16_t)0x0100) /*!< FLTDIV1 */
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#define Port_FLTFTM1FLTDIV2 ((uint16_t)0x0200) /*!< FLTDIV2 */
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#define Port_FLTFTM1FLTDIV3 ((uint16_t)0x0300) /*!< FLTDIV3 */
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/**
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* @}
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*/
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/** @defgroup PORT_FTM0_Filter_Division_Seclect PORTÕë¶ÔFTM0ÊäÈëÂ˲¨Ñ¡Ôñ¶¨Òå
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* @{
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*/
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#define Port_FLTFTM0NoFilter ((uint16_t)0x0000) /*!< ÎÞÂ˲¨Æ÷ */
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#define Port_FLTFTM0FLTDIV1 ((uint16_t)0x0040) /*!< FLTDIV1 */
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#define Port_FLTFTM0FLTDIV2 ((uint16_t)0x0080) /*!< FLTDIV2 */
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#define Port_FLTFTM0FLTDIV3 ((uint16_t)0x00C0) /*!< FLTDIV3 */
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/**
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* @}
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*/
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/** @defgroup PORT_IRQ_Filter_Division_Seclect PORTÕë¶ÔIRQÊäÈëÂ˲¨Ñ¡Ôñ¶¨Òå
|
* @{
|
*/
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#define Port_FLTIRQNoFilter ((uint16_t)0x0000) /*!< ÎÞÂ˲¨Æ÷ */
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#define Port_FLTIRQFLTDIV1 ((uint16_t)0x0010) /*!< Selects FLTDIV1, Stop ģʽÏÂ×Ô¶¯Çл»µ½FLTDIV3 */
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#define Port_FLTIRQFLTDIV2 ((uint16_t)0x0020) /*!< Selects FLTDIV2, Stop ģʽÏÂ×Ô¶¯Çл»µ½FLTDIV3 */
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#define Port_FLTIRQFLTDIV3 ((uint16_t)0x0030) /*!< FLTDIV3 */
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/**
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* @}
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*/
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/** @defgroup PORT_PTI_Filter_Division_Seclect PORTÕë¶ÔPTIÊäÈëÂ˲¨Ñ¡Ôñ¶¨Òå
|
* @{
|
*/
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#define Port_FLTPTIBUSCLK ((uint16_t)0x0000) /*!< BUSCLK */
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#define Port_FLTPTIFLTDIV1 ((uint16_t)0x0001) /*!< FLTDIV1 */
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#define Port_FLTPTIFLTDIV2 ((uint16_t)0x0002) /*!< FLTDIV2 */
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#define Port_FLTPTIFLTDIV3 ((uint16_t)0x0003) /*!< FLTDIV3 */
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/**
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* @}
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*/
|
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/** @defgroup PORT_PullPin_Seclect PORTÒý½ÅÉÏÀÑ¡Ôñ
|
* @{
|
*/
|
#define PORT_PTA0 0 /*!< GPIOÒý½ÅPTA0 */
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#define PORT_PTA1 1 /*!< GPIOÒý½ÅPTA1 */
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#define PORT_PTA2 2 /*!< GPIOÒý½ÅPTA2 */
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#define PORT_PTA3 3 /*!< GPIOÒý½ÅPTA3 */
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#define PORT_PTA4 4 /*!< GPIOÒý½ÅPTA4 */
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#define PORT_PTA5 5 /*!< GPIOÒý½ÅPTA5 */
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#define PORT_PTA6 6 /*!< GPIOÒý½ÅPTA6 */
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#define PORT_PTA7 7 /*!< GPIOÒý½ÅPTA7 */
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#define PORT_PTB0 8 /*!< GPIOÒý½ÅPTB0 */
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#define PORT_PTB1 9 /*!< GPIOÒý½ÅPTB1 */
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#define PORT_PTB2 10 /*!< GPIOÒý½ÅPTB2 */
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#define PORT_PTB3 11 /*!< GPIOÒý½ÅPTB3 */
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#define PORT_PTB4 12 /*!< GPIOÒý½ÅPTB4 */
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#define PORT_PTB5 13 /*!< GPIOÒý½ÅPTB5 */
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#define PORT_PTB6 14 /*!< GPIOÒý½ÅPTB6 */
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#define PORT_PTB7 15 /*!< GPIOÒý½ÅPTB7 */
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#define PORT_PTC0 16 /*!< GPIOÒý½ÅPTC0 */
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#define PORT_PTC1 17 /*!< GPIOÒý½ÅPTC1 */
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#define PORT_PTC2 18 /*!< GPIOÒý½ÅPTC2 */
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#define PORT_PTC3 19 /*!< GPIOÒý½ÅPTC3 */
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#define PORT_PTC4 20 /*!< GPIOÒý½ÅPTC4 */
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#define PORT_PTC5 21 /*!< GPIOÒý½ÅPTC5 */
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#define PORT_PTC6 22 /*!< GPIOÒý½ÅPTC6 */
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#define PORT_PTC7 23 /*!< GPIOÒý½ÅPTC7 */
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#define PORT_PTD0 24 /*!< GPIOÒý½ÅPTD0 */
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#define PORT_PTD1 25 /*!< GPIOÒý½ÅPTD1 */
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#define PORT_PTD2 26 /*!< GPIOÒý½ÅPTD2 */
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#define PORT_PTD3 27 /*!< GPIOÒý½ÅPTD3 */
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#define PORT_PTD4 28 /*!< GPIOÒý½ÅPTD4 */
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#define PORT_PTD5 29 /*!< GPIOÒý½ÅPTD5 */
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#define PORT_PTD6 30 /*!< GPIOÒý½ÅPTD6 */
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#define PORT_PTD7 31 /*!< GPIOÒý½ÅPTD7 */
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/* in GPIOB register */
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#define PORT_PTE0 32 /*!< GPIOÒý½ÅPTE0 */
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#define PORT_PTE1 33 /*!< GPIOÒý½ÅPTE1 */
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#define PORT_PTE2 34 /*!< GPIOÒý½ÅPTE2 */
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#define PORT_PTE3 35 /*!< GPIOÒý½ÅPTE3 */
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#define PORT_PTE4 36 /*!< GPIOÒý½ÅPTE4 */
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#define PORT_PTE5 37 /*!< GPIOÒý½ÅPTE5 */
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#define PORT_PTE6 38 /*!< GPIOÒý½ÅPTE6 */
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#define PORT_PTE7 39 /*!< GPIOÒý½ÅPTE7 */
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#define PORT_PTF0 40 /*!< GPIOÒý½ÅPTF0 */
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#define PORT_PTF1 41 /*!< GPIOÒý½ÅPTF1 */
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#define PORT_PTF2 42 /*!< GPIOÒý½ÅPTF2 */
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#define PORT_PTF3 43 /*!< GPIOÒý½ÅPTF3 */
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#define PORT_PTF4 44 /*!< GPIOÒý½ÅPTF4 */
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#define PORT_PTF5 45 /*!< GPIOÒý½ÅPTF5 */
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#define PORT_PTF6 46 /*!< GPIOÒý½ÅPTF6 */
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#define PORT_PTF7 47 /*!< GPIOÒý½ÅPTF7 */
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#define PORT_PTG0 48 /*!< GPIOÒý½ÅPTG0 */
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#define PORT_PTG1 49 /*!< GPIOÒý½ÅPTG1 */
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#define PORT_PTG2 50 /*!< GPIOÒý½ÅPTG2 */
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#define PORT_PTG3 51 /*!< GPIOÒý½ÅPTG3 */
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#define PORT_PTG4 52 /*!< GPIOÒý½ÅPTG4 */
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#define PORT_PTG5 53 /*!< GPIOÒý½ÅPTG5 */
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#define PORT_PTG6 54 /*!< GPIOÒý½ÅPTG6 */
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#define PORT_PTG7 55 /*!< GPIOÒý½ÅPTG7 */
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#define PORT_PTH0 56 /*!< GPIOÒý½ÅPTH0 */
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#define PORT_PTH1 57 /*!< GPIOÒý½ÅPTH1 */
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#define PORT_PTH2 58 /*!< GPIOÒý½ÅPTH2 */
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#define PORT_PTH3 59 /*!< GPIOÒý½ÅPTH3 */
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#define PORT_PTH4 60 /*!< GPIOÒý½ÅPTH4 */
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#define PORT_PTH5 61 /*!< GPIOÒý½ÅPTH5 */
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#define PORT_PTH6 62 /*!< GPIOÒý½ÅPTH6 */
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#define PORT_PTH7 63 /*!< GPIOÒý½ÅPTH7 */
|
/* in GPIOC register */
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#define PORT_PTI0 64 /*!< GPIOÒý½ÅPTI0 */
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#define PORT_PTI1 65 /*!< GPIOÒý½ÅPTI1 */
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#define PORT_PTI2 66 /*!< GPIOÒý½ÅPTI2 */
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#define PORT_PTI3 67 /*!< GPIOÒý½ÅPTI3 */
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#define PORT_PTI4 68 /*!< GPIOÒý½ÅPTI4 */
|
#define PORT_PTI5 69 /*!< GPIOÒý½ÅPTI5 */
|
#define PORT_PTI6 70 /*!< GPIOÒý½ÅPTI6 */
|
/**
|
* @}
|
*/
|
|
/** @defgroup PORT_HighDrive_Seclect PORT´óµçÁ÷Çý¶¯Òý½Å¶¨Òå
|
* @{
|
*/
|
#define PORT_PullPTB4 0 /*!< Òý½ÅPTB4 */
|
#define PORT_PullPTB5 1 /*!< Òý½ÅPTB5 */
|
#define PORT_PullPTD0 2 /*!< Òý½ÅPTD0 */
|
#define PORT_PullPTD1 3 /*!< Òý½ÅPTD1 */
|
#define PORT_PullPTE0 4 /*!< Òý½ÅPTE0 */
|
#define PORT_PullPTE1 5 /*!< Òý½ÅPTE1 */
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#define PORT_PullPTH0 6 /*!< Òý½ÅPTH0 */
|
#define PORT_PullPTH1 7 /*!< Òý½ÅPTH1 */
|
/**
|
* @}
|
*/
|
|
|
|
/**
|
* @}
|
*/
|
|
/* Exported macro ------------------------------------------------------------*/
|
/* Exported functions --------------------------------------------------------*/
|
void PORT_DeInit(void);
|
void PORT_IOFLT0Config(const port_ioflt0_config *IOflt0ConfigPtr);
|
void PORT_IOFLT1Config(const port_ioflt1_config *IOflt1ConfigPtr);
|
void PORT_FLTDIV3ConSet(uint32_t clk);
|
void PORT_FLTDIV2Set(uint32_t clk);
|
void PORT_FLTDIV1Set(uint32_t clk);
|
void PORT_FLTNMISET(uint32_t NMIFilter);
|
void PORT_FLTKBI1SET(uint32_t KBI1Filter);
|
void PORT_FLTKBI0SET(uint32_t KBI0Filter);
|
void PORT_FLTRSTSET(uint32_t RSTFilter);
|
void PORT_FLTISET(uint32_t FLTIFilter);
|
void PORT_FLTHSET(uint32_t FLTHFilter);
|
void PORT_FLTGSET(uint32_t FLTGFilter);
|
void PORT_FLTFSET(uint32_t FLTFFilter);
|
void PORT_FLTESET(uint32_t FLTEFilter);
|
void PORT_FLTDSET(uint32_t FLTDFilter);
|
void PORT_FLTCSET(uint32_t FLTCFilter);
|
void PORT_FLTBSET(uint32_t FLTBFilter);
|
void PORT_FLTASET(uint32_t FLTAFilter);
|
void PORT_FLTEWMSET(uint32_t FLTEWMFilter);
|
void PORT_FLTI2C1SET(uint32_t FLTI2C1Filter);
|
void PORT_FLTI2C0SET(uint32_t FLTI2C0Filter);
|
void PORT_FLTPWTSET(uint32_t FLTPWTFilter);
|
void PORT_FLTFTM1SET(uint32_t FLTFTM1Filter);
|
void PORT_FLTFTM0SET(uint32_t FLTFTM0Filter);
|
void PORT_FLTIRQSET(uint32_t FLTIRQFilter);
|
void PORT_PullPinCmd(uint8_t PortPin,FunctionalState NewState);
|
void PORT_HDRVEPinCmd(uint8_t hdrvePin,FunctionalState NewState);
|
|
|
#ifdef __cplusplus
|
}
|
#endif
|
|
#endif /* __XL_PORT_H */
|
/**
|
* @}
|
*/
|
|
/**
|
* @}
|
*/
|
