/**
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******************************************************************************
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* @file xl_spi.h
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* @author software group
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* @brief This file contains all the functions prototypes for the SPI
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* firmware library.
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******************************************************************************
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* @attention
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*
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* 2019 by Chipways Communications,Inc. All Rights Reserved.
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* This software is supplied under the terms of a license
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* agreement or non-disclosure agreement with Chipways.
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* Passing on and copying of this document,and communication
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* of its contents is not permitted without prior written
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* authorization.
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*
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* <h2><center>© COPYRIGHT 2019 Chipways</center></h2>
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******************************************************************************
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*/
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#ifndef XL_SPI_H_
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#define XL_SPI_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ---------------------------------------------------------------*/
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#include "XL6600.h"
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/* Register define ------------------------------------------------------------*/
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/* CTRLR0 Bit Fields */
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#define SPI_CTRLR0_DFS_MASK 0xFu
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#define SPI_CTRLR0_DFS_SHIFT 0
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#define SPI_CTRLR0_SCPH_MASK 0x40u
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#define SPI_CTRLR0_SCPH_SHIFT 6
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#define SPI_CTRLR0_SCPOL_MASK 0x80u
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#define SPI_CTRLR0_SCPOL_SHIFT 7
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#define SPI_CTRLR0_TMOD_MASK 0x300u
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#define SPI_CTRLR0_TMOD_SHIFT 8
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#define SPI_CTRLR0_SLVOE_MASK 0x400u
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#define SPI_CTRLR0_SLVOE_SHIFT 10
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#define SPI_CTRLR0_SRL_MASK 0x800u
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#define SPI_CTRLR0_SRL_SHIFT 11
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/* CTRLR1 Bit Fields */
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#define SPI_CTRLR1_NDF_MASK 0xFFFFu
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#define SPI_CTRLR1_NDF_SHIFT 0
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/* SPIENR Bit Fields */
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#define SPI_SPIENR_SPIE_MASK 0x1u
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#define SPI_SPIENR_SPIE_SHIFT 0
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/* SER Bit Fields */
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#define SPI_SER_SSEF_MASK 0x1u
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#define SPI_SER_SSEF_SHIFT 0
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/* BAUDR Bit Fields */
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#define SPI_BAUDR_SCKDV_MASK 0xFFFFu
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#define SPI_BAUDR_SCKDV_SHIFT 0
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/* TXFTLR Bit Fields */
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#define SPI_TXFTLR_TFTL_MASK 0xFu
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#define SPI_TXFTLR_TFTL_SHIFT 0
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/* RXFTLR Bit Fields */
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#define SPI_RXFTLR_RFTL_MASK 0xFu
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#define SPI_RXFTLR_RFTL_SHIFT 0
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/* TXFLR Bit Fields */
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#define SPI_TXFLR_TFL_MASK 0x1Fu
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#define SPI_TXFLR_TFL_SHIFT 0
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/* RXFLR Bit Fields */
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#define SPI_RXFLR_RFL_MASK 0x1Fu
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#define SPI_RXFLR_RFL_SHIFT 0
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/* SR Bit Fields */
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#define SPI_SR_BUSY_MASK 0x1u
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#define SPI_SR_BUSY_SHIFT 0
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#define SPI_SR_TFNF_MASK 0x2u
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#define SPI_SR_TFNF_SHIFT 1
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#define SPI_SR_TFE_MASK 0x4u
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#define SPI_SR_TFE_SHIFT 2
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#define SPI_SR_RFNE_MASK 0x8u
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#define SPI_SR_RFNE_SHIFT 3
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#define SPI_SR_RFF_MASK 0x10u
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#define SPI_SR_RFF_SHIFT 4
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#define SPI_SR_TXE_MASK 0x20u
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#define SPI_SR_TXE_SHIFT 5
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#define SPI_SR_DCOL_MASK 0x40u
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#define SPI_SR_DCOL_SHIFT 6
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/* IMR Bit Fields */
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#define SPI_IMR_TXEIM_MASK 0x1u
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#define SPI_IMR_TXEIM_SHIFT 0
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#define SPI_IMR_TXOIM_MASK 0x2u
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#define SPI_IMR_TXOIM_SHIFT 1
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#define SPI_IMR_RXUIM_MASK 0x4u
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#define SPI_IMR_RXUIM_SHIFT 2
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#define SPI_IMR_RXOIM_MASK 0x8u
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#define SPI_IMR_RXOIM_SHIFT 3
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#define SPI_IMR_RXFIM_MASK 0x10u
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#define SPI_IMR_RXFIM_SHIFT 4
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/* ISR Bit Fields */
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#define SPI_ISR_TXEIS_MASK 0x1u
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#define SPI_ISR_TXEIS_SHIFT 0
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#define SPI_ISR_TXOIS_MASK 0x2u
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#define SPI_ISR_TXOIS_SHIFT 1
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#define SPI_ISR_RXUIS_MASK 0x4u
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#define SPI_ISR_RXUIS_SHIFT 2
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#define SPI_ISR_RXOIS_MASK 0x8u
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#define SPI_ISR_RXOIS_SHIFT 3
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#define SPI_ISR_RXFIS_MASK 0x10u
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#define SPI_ISR_RXFIS_SHIFT 4
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/* RISR Bit Fields */
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#define SPI_RISR_TXEIR_MASK 0x1u
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#define SPI_RISR_TXEIR_SHIFT 0
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#define SPI_RISR_TXOIR_MASK 0x2u
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#define SPI_RISR_TXOIR_SHIFT 1
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#define SPI_RISR_RXUIR_MASK 0x4u
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#define SPI_RISR_RXUIR_SHIFT 2
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#define SPI_RISR_RXOIR_MASK 0x8u
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#define SPI_RISR_RXOIR_SHIFT 3
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#define SPI_RISR_RXFIR_MASK 0x10u
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#define SPI_RISR_RXFIR_SHIFT 4
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/* TXOICR Bit Fields */
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#define SPI_TXOICR_CTXOI_MASK 0x1u
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#define SPI_TXOICR_CTXOI_SHIFT 0
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/* RXOICR Bit Fields */
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#define SPI_RXOICR_CRXOI_MASK 0x1u
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#define SPI_RXOICR_CRXOI_SHIFT 0
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/* RXUICR Bit Fields */
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#define SPI_RXUICR_CRXUI_MASK 0x1u
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#define SPI_RXUICR_CRXUI_SHIFT 0
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/* ICR Bit Fields */
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#define SPI_ICR_CI_MASK 0x1u
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#define SPI_ICR_CI_SHIFT 0
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/* DMACR Bit Fields */
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#define SPI_DMACR_RDMAE_MASK 0x1u
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#define SPI_DMACR_RDMAE_SHIFT 0
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#define SPI_DMACR_TDMAE_MASK 0x2u
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#define SPI_DMACR_TDMAE_SHIFT 1
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/* DMATDLR Bit Fields */
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#define SPI_DMATDLR_DMATDL_MASK 0xFu
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#define SPI_DMATDLR_DMATDL_SHIFT 0
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#define SPI_DMATDLR_DMATDL_WIDTH 4
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/* DMARDLR Bit Fields */
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#define SPI_DMARDLR_DMARDL_MASK 0xFu
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#define SPI_DMARDLR_DMARDL_SHIFT 0
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/* DR Bit Fields */
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#define SPI_DR_DR_MASK 0xFFFFu
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#define SPI_DR_DR_SHIFT 0
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/* MODE Bit Fields */
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#define SPI_MODE_MSTR_MASK 0x1u
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#define SPI_MODE_MSTR_SHIFT 0
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/* MODE Bit Fields */
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#define SPI_MODE_PACK_MASK 0x2u
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#define SPI_MODE_PACK_SHIFT 1
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/** SPI - Register Layout Typedef */
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typedef struct {
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__IO uint32_t CTRLR0; /*!< SPI¿ØÖƼĴæÆ÷0, offset:0x0*/
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__IO uint32_t CTRLR1; /*!< SPI¿ØÖƼĴæÆ÷1, offset:0x04*/
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__IO uint32_t SPIENR; /*!< SPIʹÄܼĴæÆ÷, offset:0x08*/
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uint32_t RESERVED_0[1];
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__IO uint32_t SER; /*!< SPI´Ó»úʹÄܼĴæÆ÷, offset:0x10*/
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__IO uint32_t BAUDR; /*!< SPI²¨ÌØÂÊÑ¡Ôñ¼Ä´æÆ÷, offset:0x14*/
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__IO uint32_t TXFTLR; /*!< SPI·¢ËÍFIFOãÐÖµÉèÖüĴæÆ÷, offset:0x18*/
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__IO uint32_t RXFTLR; /*!< SPI½ÓÊÕFIFOãÐÖµÉèÖüĴæÆ÷, offset:0x1C*/
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__I uint32_t TXFLR; /*!< SPI·¢ËÍFIFOãÐÖµ¼Ä´æÆ÷, offset:0x20*/
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__I uint32_t RXFLR; /*!< SPI½ÓÊÕFIFOãÐÖµ¼Ä´æÆ÷, offset:0x24*/
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__I uint32_t SR; /*!< SPI״̬¼Ä´æÆ÷, offset:0x28*/
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__IO uint32_t IMR; /*!< SPIÖжÏÆÁ±Î¼Ä´æÆ÷, offset:0x2C*/
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__I uint32_t ISR; /*!< SPIÖжÏ״̬¼Ä´æÆ÷, offset:0x30*/
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__I uint32_t RISR; /*!< SPIÔʼÖжÏ״̬¼Ä´æÆ÷, offset:0x34*/
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__I uint32_t TXOICR; /*!< SPI·¢ËÍFIFOÒç³öÖжÏÇåÁã¼Ä´æÆ÷, offset:0x38*/
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__I uint32_t RXOICR; /*!< SPI½ÓÊÕFIFOÒç³öÖжÏÇåÁã¼Ä´æÆ÷, offset:0x3C*/
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