/**
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******************************************************************************
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* @file xl_i2c.h
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* @author software group
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* @brief This file contains all the functions prototypes for the I2C
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* firmware library.
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******************************************************************************
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* @attention
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*
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* 2019 by Chipways Communications,Inc. All Rights Reserved.
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* This software is supplied under the terms of a license
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* agreement or non-disclosure agreement with Chipways.
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* Passing on and copying of this document,and communication
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* of its contents is not permitted without prior written
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* authorization.
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*
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* <h2><center>© COPYRIGHT 2019 Chipways</center></h2>
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******************************************************************************
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*/
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#ifndef __XL_I2C_H__
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#define __XL_I2C_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Define to prevent recursive inclusion -------------------------------------*/
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#include "XL6600.h"
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/* Register define ------------------------------------------------------------*/
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/* I2C_CR Bit Fields */
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#define I2C_CR_ME_MASK 0x1u
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#define I2C_CR_ME_SHIFT 0
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#define I2C_CR_SPEED_MASK 0x6u
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#define I2C_CR_SPEED_SHIFT 2
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#define I2C_CR_SAD_MASK 0x8u
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#define I2C_CR_SAD_SHIFT 3
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#define I2C_CR_MAD_MASK 0x10u
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#define I2C_CR_MAD_SHIFT 4
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#define I2C_CR_RE_MASK 0x20u
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#define I2C_CR_RE_SHIFT 5
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#define I2C_CR_SD_MASK 0x40u
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#define I2C_CR_SD_SHIFT 6
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/* I2C_TAR Bit Fields */
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#define I2C_TAR_TAD_MASK 0x3FFu
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#define I2C_TAR_TAD_SHIFT 0
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#define I2C_TAR_GOS_MASK 0x400u
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#define I2C_TAR_GOS_SHIFT 10
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#define I2C_TAR_SPECIAL_MASK 0x800u
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#define I2C_TAR_SPECIAL_SHIFT 11
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/* I2C_SAR Bit Fields */
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#define I2C_SAR_SAD_MASK 0x3FFu
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#define I2C_SAR_SAD_SHIFT 0
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/* I2C_HSMA Bit Fields */
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#define I2C_HSMA_HSMC_MASK 0x7u
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#define I2C_HSMA_HSMC_SHIFT 0
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/* I2C_DBC Bit Fields */
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#define I2C_DBC_DAT_MASK 0xFFu
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#define I2C_DBC_DAT_SHIFT 0
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#define I2C_DBC_CMD_MASK 0x100u
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#define I2C_DBC_CMD_SHIFT 8
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#define I2C_DBC_STOP_MASK 0x200u
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#define I2C_DBC_STOP_SHIFT 9
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#define I2C_DBC_RESTART_MASK 0x400u
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#define I2C_DBC_RESTART_SHIFT 10
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/* I2C_SSCH Bit Fields */
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#define I2C_SSCH_HCNT_MASK 0xFFFFu
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#define I2C_SSCH_HCNT_SHIFT 0
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/* I2C_SSCL Bit Fields */
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#define I2C_SSCL_LCNT_MASK 0xFFFFu
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#define I2C_SSCL_LCNT_SHIFT 0
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/* I2C_FSCH Bit Fields */
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#define I2C_FSCH_HCNT_MASK 0xFFFFu
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#define I2C_FSCH_HCNT_SHIFT 0
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/* I2C_FSCL Bit Fields */
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#define I2C_FSCL_LCNT_MASK 0xFFFFu
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#define I2C_FSCL_LCNT_SHIFT 0
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/* I2C_HSCH Bit Fields */
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#define I2C_HSCH_HCNT_MASK 0xFFFFu
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#define I2C_HSCH_HCNT_SHIFT 0
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/* I2C_HSCL Bit Fields */
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#define I2C_HSCL_LCNT_MASK 0xFFFFu
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#define I2C_HSCL_LCNT_SHIFT 0
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/* I2C_IS Bit Fields */
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#define I2C_IS_RU_MASK 0x1u
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#define I2C_IS_RU_SHIFT 0
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#define I2C_IS_RO_MASK 0x2u
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#define I2C_IS_RO_SHIFT 1
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#define I2C_IS_RF_MASK 0x4u
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#define I2C_IS_RF_SHIFT 2
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#define I2C_IS_TO_MASK 0x8u
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#define I2C_IS_TO_SHIFT 3
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#define I2C_IS_TEMP_MASK 0x10u
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#define I2C_IS_TEMP_SHIFT 4
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#define I2C_IS_RDREQ_MASK 0x20u
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#define I2C_IS_RDREQ_SHIFT 5
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#define I2C_IS_TABT_MASK 0x40u
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#define I2C_IS_TABT_SHIFT 6
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#define I2C_IS_RD_MASK 0x80u
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#define I2C_IS_RD_SHIFT 7
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#define I2C_IS_ACT_MASK 0x100u
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#define I2C_IS_ACT_SHIFT 8
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#define I2C_IS_STPD_MASK 0x200u
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#define I2C_IS_STPD_SHIFT 9
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#define I2C_IS_STATD_MASK 0x400u
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#define I2C_IS_STATD_SHIFT 10
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#define I2C_IS_GC_MASK 0x800u
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#define I2C_IS_GC_SHIFT 11
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/* I2C_INTRM Bit Fields */
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#define I2C_INTRM_RU_MASK 0x1u
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#define I2C_INTRM_RU_SHIFT 0
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#define I2C_INTRM_RO_MASK 0x2u
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#define I2C_INTRM_RO_SHIFT 1
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#define I2C_INTRM_RF_MASK 0x4u
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#define I2C_INTRM_RF_SHIFT 2
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#define I2C_INTRM_TO_MASK 0x8u
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#define I2C_INTRM_TO_SHIFT 3
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#define I2C_INTRM_TEMP_MASK 0x10u
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#define I2C_INTRM_TEMP_SHIFT 4
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#define I2C_INTRM_RDREQ_MASK 0x20u
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#define I2C_INTRM_RDREQ_SHIFT 5
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#define I2C_INTRM_TABT_MASK 0x40u
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#define I2C_INTRM_TABT_SHIFT 6
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#define I2C_INTRM_RD_MASK 0x80u
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#define I2C_INTRM_RD_SHIFT 7
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#define I2C_INTRM_ACT_MASK 0x100u
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#define I2C_INTRM_ACT_SHIFT 8
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#define I2C_INTRM_STPD_MASK 0x200u
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#define I2C_INTRM_STPD_SHIFT 9
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#define I2C_INTRM_STATD_MASK 0x400u
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#define I2C_INTRM_STATD_SHIFT 10
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#define I2C_INTRM_GC_MASK 0x800u
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#define I2C_INTRM_GC_SHIFT 11
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/* I2C_RIS Bit Fields */
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#define I2C_RIS_RU_MASK 0x1u
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#define I2C_RIS_RU_SHIFT 0
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#define I2C_RIS_RO_MASK 0x2u
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#define I2C_RIS_RO_SHIFT 1
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#define I2C_RIS_RF_MASK 0x4u
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#define I2C_RIS_RF_SHIFT 2
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#define I2C_RIS_TO_MASK 0x8u
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#define I2C_RIS_TO_SHIFT 3
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#define I2C_RIS_TEMP_MASK 0x10u
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#define I2C_RIS_TEMP_SHIFT 4
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#define I2C_RIS_RDREQ_MASK 0x20u
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#define I2C_RIS_RDREQ_SHIFT 5
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#define I2C_RIS_TABT_MASK 0x40u
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#define I2C_RIS_TABT_SHIFT 6
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#define I2C_RIS_RD_MASK 0x80u
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#define I2C_RIS_RD_SHIFT 7
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#define I2C_RIS_ACT_MASK 0x100u
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#define I2C_RIS_ACT_SHIFT 8
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#define I2C_RIS_STPD_MASK 0x200u
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#define I2C_RIS_STPD_SHIFT 9
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#define I2C_RIS_STATD_MASK 0x400u
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#define I2C_RIS_STATD_SHIFT 10
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#define I2C_RIS_GC_MASK 0x800u
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#define I2C_RIS_GC_SHIFT 11
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/* I2C_RXTL Bit Fields */
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#define I2C_RXTL_RFTL_MASK 0xFFu
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#define I2C_RXTL_RFTL_SHIFT 0
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/* I2C_TXTL Bit Fields */
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#define I2C_TXTL_TFTL_MASK 0xFFu
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#define I2C_TXTL_TFTL_SHIFT 0
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/* I2C_CCI Bit Fields */
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#define I2C_CCI_CI_MASK 0x1u
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#define I2C_CCI_CI_SHIFT 0
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/* I2C_CRU Bit Fields */
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#define I2C_CRU_CRUI_MASK 0x1u
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#define I2C_CRU_CRUI_SHIFT 0
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/* I2C_CRO Bit Fields */
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#define I2C_CRO_CROI_MASK 0x1u
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#define I2C_CRO_CROI_SHIFT 0
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/* I2C_CTO Bit Fields */
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#define I2C_CTO_CTOI_MASK 0x1u
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#define I2C_CTO_CTOI_SHIFT 0
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/* I2C_CRR Bit Fields */
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#define I2C_CRR_CRRI_MASK 0x1u
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#define I2C_CRR_CRRI_SHIFT 0
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/* I2C_CTXA Bit Fields */
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#define I2C_CTXA_CTABTI_MASK 0x1u
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#define I2C_CTXA_CTABTI_SHIFT 0
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/* I2C_CRD Bit Fields */
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#define I2C_CRD_CRDI_MASK 0x1u
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#define I2C_CRD_CRDI_SHIFT 0
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/* I2C__CACT Bit Fields */
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#define I2C_CACT_CACT_MASK 0x1u
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#define I2C_CACT_CACT_SHIFT 0
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/* I2C_CSTOP Bit Fields */
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#define I2C_CSTOP_CSTPD_MASK 0x1u
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#define I2C_CSTOP_CSTPD_SHIFT 0
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/* I2C_CSTART Bit Fields */
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#define I2C_CSTART_CSTATD_MASK 0x1u
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#define I2C_CSTART_CSTATD_SHIFT 0
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/* I2C_CGC Bit Fields */
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#define I2C_CGC_CGC_MASK 0x1u
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#define I2C_CGC_CGC_SHIFT 0
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/* I2C_ENABLE Bit Fields */
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#define I2C_ENABLE_EN_MASK 0x1u
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#define I2C_ENABLE_EN_SHIFT 0
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/* I2C_STATUS Bit Fields */
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#define I2C_STATUS_ACT_MASK 0x1u
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#define I2C_STATUS_ACT_SHIFT 0
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#define I2C_STATUS_TFNF_MASK 0x2u
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#define I2C_STATUS_TFNF_SHIFT 1
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#define I2C_STATUS_TFE_MASK 0x4u
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#define I2C_STATUS_TFE_SHIFT 2
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#define I2C_STATUS_RFNE_MASK 0x8u
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#define I2C_STATUS_RFNE_SHIFT 3
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#define I2C_STATUS_RFF_MASK 0x10u
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#define I2C_STATUS_RFF_SHIFT 4
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#define I2C_STATUS_MACT_MASK 0x20u
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#define I2C_STATUS_MACT_SHIFT 5
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#define I2C_STATUS_SACT_MASK 0x40u
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#define I2C_STATUS_SACT_SHIFT 6
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/* I2C_TXFLR Bit Fields */
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#define I2C_TXFLR_TXFL_MASK 0xFu
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#define I2C_TXFLR_TXFL_SHIFT 0
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/* I2C_RXFLR Bit Fields */
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#define I2C_RXFLR_RXFL_MASK 0xFu
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#define I2C_RXFLR_RXFL_SHIFT 0
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/* I2C_TXAS Bit Fields */
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#define I2C_TXAS_A7ADN_MASK 0x1u
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#define I2C_TXAS_A7ADN_SHIFT 0
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#define I2C_TXAS_A10AD1N_MASK 0x2u
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#define I2C_TXAS_A10AD1N_SHIFT 1
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#define I2C_TXAS_A10AD2N_MASK 0x4u
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#define I2C_TXAS_A10AD2N_SHIFT 2
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#define I2C_TXAS_ATXDN_MASK 0x8u
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#define I2C_TXAS_ATXDN_SHIFT 3
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#define I2C_TXAS_AGCN_MASK 0x10u
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#define I2C_TXAS_AGCN_SHIFT 4
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#define I2C_TXAS_AGCR_MASK 0x20u
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#define I2C_TXAS_AGCR_SHIFT 5
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#define I2C_TXAS_AHSA_MASK 0x40u
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#define I2C_TXAS_AHSA_SHIFT 6
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#define I2C_TXAS_ASBA_MASK 0x80u
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#define I2C_TXAS_ASBA_SHIFT 7
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#define I2C_TXAS_AHSNS_MASK 0x100u
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#define I2C_TXAS_AHSNS_SHIFT 8
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#define I2C_TXAS_ASBNS_MASK 0x200u
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#define I2C_TXAS_ASBNS_SHIFT 9
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#define I2C_TXAS_A10BNS_MASK 0x400u
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#define I2C_TXAS_A10BNS_SHIFT 10
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#define I2C_TXAS_AMD_MASK 0x800u
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#define I2C_TXAS_AMD_SHIFT 11
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#define I2C_TXAS_AL_MASK 0x1000u
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#define I2C_TXAS_AL_SHIFT 12
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#define I2C_TXAS_AST_MASK 0x2000u
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#define I2C_TXAS_AST_SHIFT 13
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#define I2C_TXAS_ASA_MASK 0x4000u
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#define I2C_TXAS_ASA_SHIFT 14
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#define I2C_TXAS_ASI_MASK 0x8000u
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#define I2C_TXAS_ASI_SHIFT 15
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/* I2C_SDAS Bit Fields */
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#define I2C_SDAS_SDAS_MASK 0xFFu
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#define I2C_SDAS_SDAS_SHIFT 0
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/* I2C_AGC Bit Fields */
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#define I2C_AGC_ACKGC_MASK 0x1u
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#define I2C_AGC_ACKGC_SHIFT 0
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/* I2C_ES Bit Fields */
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#define I2C_ES_ENS_MASK 0x1u
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#define I2C_ES_ENS_SHIFT 0
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#define I2C_ES_SROA_MASK 0x2u
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#define I2C_ES_SROA_SHIFT 1
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#define I2C_ES_SFFF_MASK 0x4u
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#define I2C_ES_SFFF_SHIFT 2
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/** I2C - Register Layout Typedef */
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typedef struct {
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__IO uint32_t CR; /**<I2C¿ØÖƼĴæÆ÷, offset: 0x00*/
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__IO uint32_t TAR; /**<I2CÄ¿±êµØÖ·¼Ä´æÆ÷, offset: 0x04*/
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__IO uint32_t SAR; /**<I2C´ÓµØÖ·¼Ä´æÆ÷, offset: 0x08*/
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uint32_t RESERVED1;
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__IO uint32_t DBC; /**<I2CÊý¾ÝºÍÃüÁî¼Ä´æÆ÷, offset: 0x10*/
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__IO uint32_t SSCH; /**<±ê×¼ËÙ¶ÈIICʱÖÓSCL¸ß¼ÆÊý¼Ä´æÆ÷, offset: 0x14*/
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__IO uint32_t SSCL; /**<±ê×¼ËÙ¶ÈI2CʱÖÓSCLµÍ¼ÆÊý¼Ä´æÆ÷, offset: 0x18*/
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__IO uint32_t FSCH; /**<¿ìËÙI2CʱÖÓSCL¸ß¼ÆÊý¼Ä´æÆ÷, offset: 0x1C*/
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__IO uint32_t FSCL; /**<¿ìËÙI2CʱÖÓSCLµÍ¼ÆÊý¼Ä´æÆ÷, offset: 0x20*/
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uint32_t RESERVED2[2];
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__I uint32_t IS; /**<I2CÖжÏ״̬¼Ä´æÆ÷, offset: 0x2C*/
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__IO uint32_t INTRM; /**<I2CÖжÏÆÁ±Î¼Ä´æÆ÷, offset: 0x30*/
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__I uint32_t RIS; /**<I2CÔʼÖжÏ״̬¼Ä´æÆ÷, offset: 0x34*/
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__IO uint32_t RXTL; /**<I2C½ÓÊÕFIFOãÐÖµ¼Ä´æÆ÷, offset: 0x38*/
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__IO uint32_t TXTL; /**<I2C·¢ËÍFIFOãÐÖµ¼Ä´æÆ÷, offset: 0x3C*/
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__I uint32_t CCI; /**<ÇåÁãËùÓÐÖжϼĴæÆ÷, offset: 0x40*/
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__I uint32_t CRU; /**<ÇåÁã½ÓÊÕÏÂÒçÖжϼĴæÆ÷, offset: 0x44*/
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__I uint32_t CRO; /**<ÇåÁã½ÓÊÕÒç³öÖжϼĴæÆ÷, offset: 0x48*/
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__I uint32_t CTO; /**<ÇåÁã·¢ËÍÒç³öÖжϼĴæÆ÷, offset: 0x4C*/
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__I uint32_t CRR; /**<ÇåÁã¶ÁÇëÇóÖжϼĴæÆ÷, offset: 0x50*/
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__I uint32_t CTXA; /**<ÇåÁã·¢ËÍÖÐÖ¹ÖжϼĴæÆ÷, offset: 0x54*/
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__I uint32_t CRD; /**<ÇåÁã½ÓÊÕÍê³ÉÖжϼĴæÆ÷, offset: 0x58*/
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__I uint32_t CACT; /**<ÇåÁã»î¶¯ÖжϼĴæÆ÷, offset: 0x5c*/
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__I uint32_t CSTOP; /**<ÇåÁãÖÕֹλ¼ì²âÖжϼĴæÆ÷, offset: 0x60*/
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__I uint32_t CSTART; /**<ÇåÁãÆðʼλ¼ì²âÖжϼĴæÆ÷, offset: 0x64*/
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__I uint32_t CGC; /**<ÇåÁãͨÓõ÷ÓÃÖжϼĴæÆ÷, offset: 0x68*/
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__IO uint32_t ENABLE; /**<I2CʹÄܼĴæÆ÷, offset: 0x6C*/
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__I uint32_t STATUS; /**<I2C״̬¼Ä´æÆ÷, offset: 0x70*/
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__I uint32_t TXFLR; /**<I2C·¢ËÍFIFOˮƽ¼Ä´æÆ÷, offset: 0x74*/
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__I uint32_t RXFLR; /**<I2C½ÓÊÕFIFOˮƽ¼Ä´æÆ÷, offset: 0x78*/
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__IO uint32_t SDAHOLD; /**<I2C SDA ±£³Öʱ¼ä³¤¶È¼Ä´æÆ÷, offset: 0x7C*/
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__IO uint32_t TXAS; /**<I2C ·¢ËÍÖÐÖ¹Ô´¼Ä´æÆ÷, offset: 0x80*/
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uint32_t RESERVED_2[4];
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__IO uint32_t SDAS; /**<I2C SDA ÉèÖüĴæÆ÷, offset: 0x94*/
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__IO uint32_t AGC; /**<I2C ACK ͨÓõ÷ÓüĴæÆ÷, offset: 0x98*/
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__I uint32_t ES; /**<I2C ʹÄÜ״̬¼Ä´æÆ÷, offset: 0x9C*/
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} I2C_Type, *I2C_MemMapPtr;
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extern I2C_Type* I2C1;
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extern I2C_Type* I2C0;
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/** @addtogroup XL6600_StdPeriph_Driver
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* @{
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*/
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/** @addtogroup I2C
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/**
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* @brief I2C³õʼ»¯½á¹¹Ì嶨Òå
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*/
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typedef struct
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{
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uint16_t I2C_SourceClk; /*!< ʱÖÓÔ´ (Mhz) */
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/* IC_CR :I2C Control Register */
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uint32_t I2C_MasterModeEn; /*!< Ö÷»úģʽÊÇ·ñʹÄÜ */
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uint32_t I2C_SlaveModeDis; /*!< ¿ØÖÆI2C´Ó»úÊÇ·ñʹÄÜ */
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uint32_t I2C_SendRestart; /*!< Ö÷»úģʽ, ÊÇ·ñÖØÆô */
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uint16_t I2C_SpeedMode; /*!< I2C²Ù×÷ËÙ¶È */
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uint32_t I2C_SADmode; /*!< ´Ó»úģʽ£¬¸Ãλ¿ØÖÆI2CÏìÓ¦7λ»ò10λµØÖ· */
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uint32_t I2C_MADmode; /*!< Ö÷»úģʽ,´Ëλ¿ØÖÆI2CÊÇÒÔ7λ»¹ÊÇ10λµØַģʽ¿ªÊ¼´«Êä */
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uint32_t I2C_TargetAddress; /*!< I2C Ä¿±êµØÖ· */
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uint32_t I2C_SlaveAddress; /*!< I2C ´Ó»úµØÖ· */
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uint16_t I2C_HSMasterModeCode; /*!< I2C¸ßËÙÖ÷»úģʽ´úÂë */
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uint32_t I2C_RXTL; /*!< I2C ½ÓÊÕFIFO ãÐÖµ */
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uint32_t I2C_TXTL; /*!< I2C ·¢ËÍFIFO ãÐÖµ */
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}I2C_InitTypeDef,*I2C_InitConfigPtr;
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/** @defgroup I2C_Function_Constants
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* @{
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*/
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/** @defgroup I2C_Master_Enable I2CÖ÷»úģʽʹÄÜ
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* @{
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*/
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#define I2C_MasterModeEnabled ((uint16_t)0x0001) /*!< 1: Ö÷»úģʽʹÄÜ */
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#define I2C_MasterModeDisabled ((uint16_t)0x0000) /*!< 0: Ö÷»úģʽʧÄÜ */
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/**
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* @}
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*/
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/** @defgroup I2C_Speed_Mode I2CËÙÂÊ
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* @{
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*/
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#define I2C_StandardMode ((uint16_t)0x0002) /*!< 1: ±ê׼ģʽ (100 kbit/s) */
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#define I2C_FastMode ((uint16_t)0x0004) /*!< 2: ¿ìËÙģʽ (400 kbit/s) */
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/**
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* @}
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*/
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/** @defgroup I2C_Slave_Address_Bit I2C´Ó»úµØַλ
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* @{
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*/
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#define I2C_10BitAddrSlave ((uint16_t)0x0008) /*!< 1: 10λµØÖ·´«Êä */
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#define I2C_7BitAddrSlave ((uint16_t)0x0000) /*!< 0: 7λµØÖ·´«Êä */
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/**
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* @}
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*/
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/** @defgroup I2C_Master_Address_Bit I2C Ö÷»úµØַλ
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* @{
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*/
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#define I2C_10BitAddrMaster ((uint16_t)0x0010) /*!< 1: 10λµØÖ·´«Êä */
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#define I2C_7BitAddrMaster ((uint16_t)0x0000) /*!< 0: 7λµØÖ·´«Êä */
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/**
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* @}
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*/
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/** @defgroup I2C_Slave_Mode_Enable I2C´Ó»úʹÄÜ
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* @{
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*/
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#define I2C_SlaveModeEnabled ((uint16_t)0x0000) /*!< 0: ´Ó»úʹÄÜ */
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#define I2C_SlaveModeDisabled ((uint16_t)0x0040) /*!< 1: ´Ó»úʧÄÜ */
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/**
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* @}
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*/
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/** @defgroup I2C_Send_Restsrt_Enable I2CÖØ·¢ÃüÁî
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* @{
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*/
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#define I2C_SendRestartDisabled ((uint16_t)0x0000) /*!< 0: I2CÖØ·¢ÃüÁîʧÄÜ */
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#define I2C_SendRestartEnabled ((uint16_t)0x0020) /*!< 1: I2CÖØ·¢ÃüÁîʹÄÜ */
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/**
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* @}
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*/
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|
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/** @defgroup High Speed Master I2C ¸ßËÙÖ÷»úģʽCode
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* @{
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*/
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#define I2C_HSMasterCode_0 ((uint16_t)0x0000) /*!< ¸ßËÙÖ÷»ú´úÂë 0*/
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#define I2C_HSMasterCode_1 ((uint16_t)0x0001) /*!< ¸ßËÙÖ÷»ú´úÂë 1*/
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#define I2C_HSMasterCode_2 ((uint16_t)0x0002) /*!< ¸ßËÙÖ÷»ú´úÂë 2*/
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#define I2C_HSMasterCode_3 ((uint16_t)0x0003) /*!< ¸ßËÙÖ÷»ú´úÂë 3*/
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#define I2C_HSMasterCode_4 ((uint16_t)0x0004) /*!< ¸ßËÙÖ÷»ú´úÂë 4*/
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#define I2C_HSMasterCode_5 ((uint16_t)0x0005) /*!< ¸ßËÙÖ÷»ú´úÂë 5*/
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#define I2C_HSMasterCode_6 ((uint16_t)0x0006) /*!< ¸ßËÙÖ÷»ú´úÂë 6*/
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#define I2C_HSMasterCode_7 ((uint16_t)0x0007) /*!< ¸ßËÙÖ÷»ú´úÂë 7*/
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/**
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* @}
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*/
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/** @defgroup I2C_Interrupt_TypeDefine I2CÖжÏÀàÐÍ
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* @{
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*/
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typedef enum
|
{
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I2C_RXUNDERInterrupt =0u, /*!< ½ÓÊÕÏÂÒçÖÐ¶Ï */
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I2C_RXOVERInterrupt , /*!< ½ÓÊÕÒç³öÖÐ¶Ï */
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I2C_RXFULLInterrupt , /*!< ½ÓÊÕÂúÖÐ¶Ï */
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I2C_TXOVERInterrupt , /*!< ·¢ËÍÒç³öÖÐ¶Ï */
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I2C_TXEMPTYInterrupt , /*!< ·¢ËÍ¿ÕÖÐ¶Ï */
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I2C_RDREQInterrupt , /*!< ¶ÁÇëÇóÖÐ¶Ï */
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I2C_TXABRTInterrupt , /*!< ·¢ËÍÖÐÖ¹ÖÐ¶Ï */
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I2C_RXDONEInterrupt , /*!< ½ÓÊÕÍê³ÉÖÐ¶Ï */
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I2C_ACTIVITYInterrupt , /*!< »î¶¯ÖÐ¶Ï */
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I2C_STOPDETInterrupt , /*!< ֹͣλ¼ì²âÖÐ¶Ï */
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I2C_STARTDETInterrupt , /*!< Æðʼλ¼ì²âÖÐ¶Ï */
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I2C_GENCALLInterrupt /*!< ͨÓõ÷ÓÃÖÐ¶Ï */
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}I2C_InterruptTypeDef;
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/**
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* @}
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*/
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/** @defgroup I2C_Interrupt_Status I2CÖжÏ״̬ÀàÐÍ
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* @{
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*/
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typedef enum {
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I2C_RXUNDERInterruptStatus =0, /*!< ½ÓÊÕÏÂÒçÖжÏ״̬ */
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I2C_RXOVERInterruptStatus , /*!< ½ÓÊÕÒç³öÖжÏ״̬ */
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I2C_RXFULLInterruptStatus , /*!< ½ÓÊÕÂúÖжÏ״̬ */
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I2C_TXOVERInterruptStatus , /*!< ·¢ËÍÒç³öÖжÏ״̬ */
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I2C_TXEMPTYInterruptStatus , /*!< ·¢ËÍ¿ÕÖжÏ״̬ */
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I2C_RDREQInterruptStatus , /*!< ¶ÁÇëÇóÖжÏ״̬ */
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I2C_TXABRTInterruptStatus , /*!< ·¢ËÍÖÐÖ¹ÖжÏ״̬ */
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I2C_RXDONEInterruptStatus , /*!< ½ÓÊÕÍê³ÉÖжÏ״̬ */
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I2C_ACTIVITYInterruptStatus , /*!< »î¶¯ÖжÏ״̬ */
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I2C_STOPDETInterruptStatus , /*!< ֹͣλ¼ì²âÖжÏ״̬ */
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I2C_STARTDETInterruptStatus , /*!< Æðʼλ¼ì²âÖжÏ״̬ */
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I2C_GENCALLInterruptStatus /*!< ͨÓõ÷ÓÃÖжÏ״̬ */
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} I2C_ITStatusMaskedDef;
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/**
|
* @}
|
*/
|
|
/** @defgroup I2C_Interrupt_RawStatus I2CÔʼÖжÏ״̬
|
* @{
|
*/
|
typedef enum {
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I2C_RXUNDERInterruptRawStatus =0, /*!< ½ÓÊÕÏÂÒçÔʼÖжÏ״̬ */
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I2C_RXOVERInterruptRawStatus , /*!< ½ÓÊÕÒç³öÔʼÖжÏ״̬ */
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I2C_RXFULLInterruptRawStatus , /*!< ½ÓÊÕÂúÔʼÖжÏ״̬ */
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I2C_TXOVERInterruptRawStatus , /*!< ·¢ËÍÒç³öÔʼÖжÏ״̬ */
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I2C_TXEMPTYInterruptRawStatus , /*!< ·¢ËÍ¿ÕÔʼÖжÏ״̬ */
|
I2C_RDREQInterruptRawStatus , /*!< ¶ÁÇëÇóÔʼÖжÏ״̬ */
|
I2C_TXABRTInterruptRawStatus , /*!< ·¢ËÍÖÐÖ¹ÔʼÖжÏ״̬ */
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I2C_RXDONEInterruptRawStatus , /*!< ½ÓÊÕÍê³ÉÔʼÖжÏ״̬ */
|
I2C_ACTIVITYInterruptRawStatus , /*!< »î¶¯ÔʼÖжÏ״̬ */
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I2C_STOPDETInterruptRawStatus , /*!< ֹͣλ¼ì²âÔʼÖжÏ״̬ */
|
I2C_STARTDETInterruptRawStatus , /*!< Æðʼλ¼ì²âÔʼÖжÏ״̬ */
|
I2C_GENCALLInterruptRawStatus /*!< ͨÓõ÷ÓÃÔʼÖжÏ״̬ */
|
} I2C_RawITStatusTypeDef;
|
/**
|
* @}
|
*/
|
|
/** @defgroup I2C_Interrupt_ClearDef I2C Çå³ýÖжϱêÖ¾
|
* @{
|
*/
|
typedef enum {
|
I2C_AllInterruptClear = 0, /*!< Çå³ýËùÓÐÖжϱêÖ¾ */
|
I2C_RXUNDERInterruptClear , /*!< Çå³ý½ÓÊÕÏÂÒçÖжϱêÖ¾ */
|
I2C_RXOVERInterruptClear , /*!< Çå³ý½ÓÊÕÒç³öÖжϱêÖ¾ */
|
I2C_TXOVERInterruptClear , /*!< Çå³ý·¢ËÍÒç³öÖжϱêÖ¾ */
|
I2C_RDREQInterruptClear , /*!< Çå³ý¶ÁÇëÇóÖжϱêÖ¾ */
|
I2C_TXABRTInterruptClear , /*!< Çå³ý·¢ËÍÖÐÖ¹ÖжϱêÖ¾ */
|
I2C_RXDONEInterruptClear , /*!< Çå³ý½ÓÊÕÍê³ÉÖжϱêÖ¾ */
|
I2C_ACTIVITYInterruptClear , /*!< Çå³ý»î¶¯ÖжϱêÖ¾ */
|
I2C_STOPDETInterruptClear , /*!< Çå³ýֹͣλ¼ì²âÖжϱêÖ¾ */
|
I2C_STARTDETInterruptClear , /*!< Çå³ýÆðʼλ¼ì²âÖжϱêÖ¾ */
|
I2C_GENCALLInterruptClear /*!< Çå³ýͨÓõ÷ÓÃÖжϱêÖ¾ */
|
|
} I2C_InterruptClearDef;
|
/**
|
* @}
|
*/
|
|
/** @defgroup I2C_Status_Register I2C״̬
|
* @{
|
*/
|
typedef enum {
|
I2C_ActivityStatus = 0, /*!< I2CÓÐЧ״̬λ */
|
I2C_TransmitFIFONotFullStatus , /*!< ½ÓÊÕFIFO²»¿Õ */
|
I2C_TransmitFIFOEmptyStatus , /*!< ·¢ËÍFIFOÍêÈ«Çå¿Õ*/
|
I2C_ReceiveFIFONotEmptyStatus , /*!< ½ÓÊÕFIFO²»¿Õ */
|
I2C_ReceiveFIFOFullStatus , /*!< ½ÓÊÕFIFOÒÑÂú */
|
I2C_MasterFSMActStatus , /*!< Ö÷»úFSMÓÐЧ״̬ */
|
I2C_SlaveFSMActStatus /*!< ´Ó»úFSMÓÐЧ״̬ */
|
} I2C_StatusTypeDef;
|
/**
|
* @}
|
*/
|
|
|
/** @defgroup I2C_TxRx_FIFO_Level I2C ·¢ËͽÓÊÕFIFOÉî¶È
|
* @{
|
*/
|
typedef enum
|
{
|
I2C_TransmitFIFOLevel = 0x00, /*!< ·¢ËÍFIFOÉî¶È */
|
I2C_ReceiveFIFOLevel = 0x01 /*!< ½ÓÊÕFIFOÉî¶È */
|
}I2C_TXRXFIFOLevelDef;
|
/**
|
* @}
|
*/
|
|
/** @defgroup I2C_Send_Stop_Def I2C ·¢ËÍstop붨Òå
|
* @{
|
*/
|
typedef enum
|
{
|
I2C_No_Stop = 0x00, /*!< I2C·¢ËͲ»Í£Ö¹ */
|
I2C_Stop = 0x01 /*!< I2C·¢ËÍÖÐÖ¹ */
|
}I2C_IsStopDef;
|
/**
|
* @}
|
*/
|
|
/** @defgroup I2C_Send_Abort_Codes I2C ·¢ËÍÖÕÖ¹µÄÔÒò¶¨Òå
|
* @{
|
*/
|
typedef enum {
|
I2C_ABRT_7B_ADDR_NOACK = 0, /*!< Ö÷»ú´¦ÓÚ7λѰַģʽ£¬·¢Ë͵ĵØַδ±»ÈκδӻúÈ·ÈÏ */
|
I2C_ABRT_10ADDR1_NOACK , /*!< Ö÷»ú´¦ÓÚ10λµØַģʽ£¬µÚÒ»¸ö10λµØÖ·×Ö½Úδ±»ÈκδӻúÈ·ÈÏ */
|
I2C_ABRT_10ADDR2_NOACK , /*!< Ö÷»ú´¦ÓÚ10λµØַģʽ£¬10λµØÖ·µÄµÚ¶þ¸öµØÖ·×Ö½Úδ±»ÈκδӻúÈ·ÈÏ */
|
I2C_ABRT_TXDATA_NOACK , /*!< I2C ·¢ËÍÎÞÓ¦´ð */
|
I2C_ABRT_GCALL_NOACK , /*!< ×ÜÏßÉÏûÓдӻúÈ·ÈÏGeneral Call */
|
I2C_ABRT_GCALL_READ , /*!< Óû§½«Í¨Óõ÷ÓúóµÄ×Ö½Ú±à³ÌΪ´Ó×ÜÏ߶ÁÈ¡ */
|
I2C_ABRT_HS_ACKDET , /*!< Ö÷»ú´¦ÓÚ¸ßËÙģʽ£¬²¢ÇÒ¸ßËÙÖ÷´úÂ뱻ȷÈÏ */
|
I2C_ABRT_SBYTE_ACKDET , /*!< Ö÷»ú·¢ËÍÁËÒ»¸öSTART×Ö½Ú£¬²¢È·ÈÏÁËSTART×Ö½Ú */
|
I2C_ABRT_HS_NORSTRT , /*!< ½ûÖ¹ÖØÐÂÆô¶¯£¨RE루I2C_CR [5]£©= 0£©£¬Óû§³¢ÊÔʹÓÃÖ÷»úÔÚ¸ßËÙģʽÏ´«ÊäÊý¾Ý */
|
I2C_ABRT_SBYTE_NORSTRT , /*!< ÊÔÇåÁãλ9֮ǰASBNSµÄÔ´²»¹Ì¶¨ */
|
I2C_ABRT_10B_RD_NORSTRT , /*!< ½ûÓÃÖØÆô£¨RE루I2C_CR [5]£©= 0£©£¬Ö÷»úÔÚ10λѰַģʽÏ·¢ËͶÁÃüÁî */
|
I2C_ABRT_MASTER_DIS , /*!< Óû§³¢ÊÔÔÚ½ûÓÃÖ÷»úģʽµÄÇé¿öÏÂÆô¶¯Ö÷»ú²Ù×÷ */
|
I2C_ARBT_LOST , /*!< ¶ªÊ§Öٲà */
|
I2C_ABRT_SLVFLUSH_TXFIFO , /*!< ´Ó»úÒѽÓÊÕµ½¶ÁÃüÁ²¢ÇÒTX FIFOÖдæÔÚһЩÊý¾Ý£¬Òò´Ë´Ó»ú·¢³öTX_ABRTÖжÏÒÔÇåÁãTX FIFOÖеľÉÊý¾Ý¡£ */
|
I2C_ABRT_SLV_ARBLOST , /*!< ´Ó»úÔÚÏòÔ¶³ÌÖ÷»ú·¢ËÍÊý¾Ýʱ¶ªÊ§×ÜÏß */
|
I2C_ABRT_SLVRD_INTX /*!< I2C×÷Ϊ´Ó·¢ËÍ£¬´¦ÀíÆ÷ÏìÓ¦´Ó»úģʽÇëÇóÒª·¢Ë͵½Ô¶³ÌÖ÷»úµÄÊý¾Ýʱ£¬Óû§ÔÚI2C_DBC¼Ä´æÆ÷µÄCMD£¨Î»8£©ÖÐдÈë1. */
|
} I2C_ABRTSourceTypeDef;
|
/**
|
* @}
|
*/
|
|
/** @defgroup I2C_Enable_Status I2CʹÄÜ״̬
|
* @{
|
*/
|
typedef enum {
|
I2C_ENStatusI2CENStatus = 0, /*!< I2CʹÄÜ״̬ */
|
I2C_ENStatusSlaveRXOperationAborted , /*!< ´Ó»ú½ÓÊÕ²Ù×÷ÖÐÖ¹ */
|
I2C_ENStatusSlaveFIFOFilledAndFlushed /*!< ´Ó»úFIFOÒÑÂú±»Ë¢Ð */
|
} I2C_EnableStatusTypeDef;
|
/**
|
* @}
|
*/
|
|
/**
|
* @}
|
*/
|
|
/* ICS exported function --------------------------------------------------------*/
|
|
void I2C_Deinit(I2C_Type *I2Cx);
|
void I2C_Init(I2C_Type *I2Cx, const I2C_InitTypeDef * I2C_InitStruct);
|
void I2C_EnableCmd(I2C_Type *I2Cx, FunctionalState NewState);
|
void I2C_GeneralCall( I2C_Type* I2Cx);
|
void I2C_GeneralCallAckEnableCmd(I2C_Type* I2Cx, FunctionalState NewState);
|
void I2C_StartByte(I2C_Type* I2Cx, uint32_t TargetAddress);
|
void I2C_InterruptEn(I2C_Type *I2Cx, const I2C_InterruptTypeDef I2C_Interrupt, FunctionalState NewState);
|
uint16_t I2C_GetMaskedIntStatus(const I2C_Type *I2Cx, I2C_ITStatusMaskedDef I2C_IntStatusType);
|
uint16_t I2C_GetRawIntgStatus(const I2C_Type *I2Cx,I2C_RawITStatusTypeDef I2C_RawIntStatusType);
|
uint16_t I2C_ClearInterrupt(const I2C_Type *I2Cx, I2C_InterruptClearDef I2C_Interrupt2Clear);
|
uint8_t I2C_GetStatus(const I2C_Type *I2Cx, I2C_StatusTypeDef I2C_StatusType);
|
uint16_t I2C_GetAbortSource(const I2C_Type *I2Cx, I2C_ABRTSourceTypeDef I2C_ABRTSourceType);
|
uint8_t I2C_GetEnableStatus(const I2C_Type *I2Cx, I2C_EnableStatusTypeDef I2C_EnableStatusType);
|
uint8_t I2C_GetFIFOLev(const I2C_Type *I2Cx, I2C_TXRXFIFOLevelDef FIFOLevelDef);
|
void I2C_WriteData(I2C_Type *I2Cx, uint8_t u8DataBuff,I2C_IsStopDef isstop);
|
void I2C_ReadDataCmd(I2C_Type *I2Cx ,I2C_IsStopDef isstop);
|
uint8_t I2C_ReadData(const I2C_Type *I2Cx);
|
void I2C_ResStartWrite(I2C_Type *I2Cx, uint8_t u8DataBuff,I2C_IsStopDef isstop);
|
void I2C_ResStartRead(I2C_Type *I2Cx);
|
void I2C_SetSDADelay(I2C_Type *I2Cx, const uint8_t I2Cclkfreq, const uint8_t DelayReq);
|
void I2C_SetSDAHoldTime(I2C_Type *I2Cx, uint16_t holdtime);
|
#ifdef __cplusplus
|
}
|
#endif
|
|
#endif
|
|
/**
|
* @}
|
*/
|
|
/**
|
* @}
|
*/
|
