/**
|
******************************************************************************
|
* @file xl_spi.h
|
* @author software group
|
* @brief This file contains all the functions prototypes for the SPI
|
* firmware library.
|
******************************************************************************
|
* @attention
|
*
|
* 2019 by Chipways Communications,Inc. All Rights Reserved.
|
* This software is supplied under the terms of a license
|
* agreement or non-disclosure agreement with Chipways.
|
* Passing on and copying of this document,and communication
|
* of its contents is not permitted without prior written
|
* authorization.
|
*
|
* <h2><center>© COPYRIGHT 2019 Chipways</center></h2>
|
******************************************************************************
|
*/
|
#ifndef XL_SPI_H_
|
#define XL_SPI_H_
|
|
#ifdef __cplusplus
|
extern "C" {
|
#endif
|
|
/* Includes ---------------------------------------------------------------*/
|
#include "XL6600.h"
|
/* Register define ------------------------------------------------------------*/
|
/* CTRLR0 Bit Fields */
|
#define SPI_CTRLR0_DFS_MASK 0xFu
|
#define SPI_CTRLR0_DFS_SHIFT 0
|
#define SPI_CTRLR0_SCPH_MASK 0x40u
|
#define SPI_CTRLR0_SCPH_SHIFT 6
|
#define SPI_CTRLR0_SCPOL_MASK 0x80u
|
#define SPI_CTRLR0_SCPOL_SHIFT 7
|
#define SPI_CTRLR0_TMOD_MASK 0x300u
|
#define SPI_CTRLR0_TMOD_SHIFT 8
|
#define SPI_CTRLR0_SLVOE_MASK 0x400u
|
#define SPI_CTRLR0_SLVOE_SHIFT 10
|
#define SPI_CTRLR0_SRL_MASK 0x800u
|
#define SPI_CTRLR0_SRL_SHIFT 11
|
|
/* CTRLR1 Bit Fields */
|
#define SPI_CTRLR1_NDF_MASK 0xFFFFu
|
#define SPI_CTRLR1_NDF_SHIFT 0
|
|
/* SPIENR Bit Fields */
|
#define SPI_SPIENR_SPIE_MASK 0x1u
|
#define SPI_SPIENR_SPIE_SHIFT 0
|
|
/* SER Bit Fields */
|
#define SPI_SER_SSEF_MASK 0x1u
|
#define SPI_SER_SSEF_SHIFT 0
|
|
/* BAUDR Bit Fields */
|
#define SPI_BAUDR_SCKDV_MASK 0xFFFFu
|
#define SPI_BAUDR_SCKDV_SHIFT 0
|
|
/* TXFTLR Bit Fields */
|
#define SPI_TXFTLR_TFTL_MASK 0xFu
|
#define SPI_TXFTLR_TFTL_SHIFT 0
|
|
/* RXFTLR Bit Fields */
|
#define SPI_RXFTLR_RFTL_MASK 0xFu
|
#define SPI_RXFTLR_RFTL_SHIFT 0
|
|
/* TXFLR Bit Fields */
|
#define SPI_TXFLR_TFL_MASK 0x1Fu
|
#define SPI_TXFLR_TFL_SHIFT 0
|
|
/* RXFLR Bit Fields */
|
#define SPI_RXFLR_RFL_MASK 0x1Fu
|
#define SPI_RXFLR_RFL_SHIFT 0
|
|
/* SR Bit Fields */
|
#define SPI_SR_BUSY_MASK 0x1u
|
#define SPI_SR_BUSY_SHIFT 0
|
#define SPI_SR_TFNF_MASK 0x2u
|
#define SPI_SR_TFNF_SHIFT 1
|
#define SPI_SR_TFE_MASK 0x4u
|
#define SPI_SR_TFE_SHIFT 2
|
#define SPI_SR_RFNE_MASK 0x8u
|
#define SPI_SR_RFNE_SHIFT 3
|
#define SPI_SR_RFF_MASK 0x10u
|
#define SPI_SR_RFF_SHIFT 4
|
#define SPI_SR_TXE_MASK 0x20u
|
#define SPI_SR_TXE_SHIFT 5
|
#define SPI_SR_DCOL_MASK 0x40u
|
#define SPI_SR_DCOL_SHIFT 6
|
|
/* IMR Bit Fields */
|
#define SPI_IMR_TXEIM_MASK 0x1u
|
#define SPI_IMR_TXEIM_SHIFT 0
|
#define SPI_IMR_TXOIM_MASK 0x2u
|
#define SPI_IMR_TXOIM_SHIFT 1
|
#define SPI_IMR_RXUIM_MASK 0x4u
|
#define SPI_IMR_RXUIM_SHIFT 2
|
#define SPI_IMR_RXOIM_MASK 0x8u
|
#define SPI_IMR_RXOIM_SHIFT 3
|
#define SPI_IMR_RXFIM_MASK 0x10u
|
#define SPI_IMR_RXFIM_SHIFT 4
|
|
/* ISR Bit Fields */
|
#define SPI_ISR_TXEIS_MASK 0x1u
|
#define SPI_ISR_TXEIS_SHIFT 0
|
#define SPI_ISR_TXOIS_MASK 0x2u
|
#define SPI_ISR_TXOIS_SHIFT 1
|
#define SPI_ISR_RXUIS_MASK 0x4u
|
#define SPI_ISR_RXUIS_SHIFT 2
|
#define SPI_ISR_RXOIS_MASK 0x8u
|
#define SPI_ISR_RXOIS_SHIFT 3
|
#define SPI_ISR_RXFIS_MASK 0x10u
|
#define SPI_ISR_RXFIS_SHIFT 4
|
|
/* RISR Bit Fields */
|
#define SPI_RISR_TXEIR_MASK 0x1u
|
#define SPI_RISR_TXEIR_SHIFT 0
|
#define SPI_RISR_TXOIR_MASK 0x2u
|
#define SPI_RISR_TXOIR_SHIFT 1
|
#define SPI_RISR_RXUIR_MASK 0x4u
|
#define SPI_RISR_RXUIR_SHIFT 2
|
#define SPI_RISR_RXOIR_MASK 0x8u
|
#define SPI_RISR_RXOIR_SHIFT 3
|
#define SPI_RISR_RXFIR_MASK 0x10u
|
#define SPI_RISR_RXFIR_SHIFT 4
|
|
/* TXOICR Bit Fields */
|
#define SPI_TXOICR_CTXOI_MASK 0x1u
|
#define SPI_TXOICR_CTXOI_SHIFT 0
|
|
/* RXOICR Bit Fields */
|
#define SPI_RXOICR_CRXOI_MASK 0x1u
|
#define SPI_RXOICR_CRXOI_SHIFT 0
|
|
/* RXUICR Bit Fields */
|
#define SPI_RXUICR_CRXUI_MASK 0x1u
|
#define SPI_RXUICR_CRXUI_SHIFT 0
|
|
/* ICR Bit Fields */
|
#define SPI_ICR_CI_MASK 0x1u
|
#define SPI_ICR_CI_SHIFT 0
|
|
/* DMACR Bit Fields */
|
#define SPI_DMACR_RDMAE_MASK 0x1u
|
#define SPI_DMACR_RDMAE_SHIFT 0
|
#define SPI_DMACR_TDMAE_MASK 0x2u
|
#define SPI_DMACR_TDMAE_SHIFT 1
|
|
/* DMATDLR Bit Fields */
|
#define SPI_DMATDLR_DMATDL_MASK 0xFu
|
#define SPI_DMATDLR_DMATDL_SHIFT 0
|
#define SPI_DMATDLR_DMATDL_WIDTH 4
|
|
/* DMARDLR Bit Fields */
|
#define SPI_DMARDLR_DMARDL_MASK 0xFu
|
#define SPI_DMARDLR_DMARDL_SHIFT 0
|
|
/* DR Bit Fields */
|
#define SPI_DR_DR_MASK 0xFFFFu
|
#define SPI_DR_DR_SHIFT 0
|
|
/* MODE Bit Fields */
|
#define SPI_MODE_MSTR_MASK 0x1u
|
#define SPI_MODE_MSTR_SHIFT 0
|
|
/* MODE Bit Fields */
|
#define SPI_MODE_PACK_MASK 0x2u
|
#define SPI_MODE_PACK_SHIFT 1
|
|
|
/** SPI - Register Layout Typedef */
|
typedef struct {
|
__IO uint32_t CTRLR0; /*!< SPI¿ØÖƼĴæÆ÷0, offset:0x0*/
|
__IO uint32_t CTRLR1; /*!< SPI¿ØÖƼĴæÆ÷1, offset:0x04*/
|
__IO uint32_t SPIENR; /*!< SPIʹÄܼĴæÆ÷, offset:0x08*/
|
uint32_t RESERVED_0[1];
|
__IO uint32_t SER; /*!< SPI´Ó»úʹÄܼĴæÆ÷, offset:0x10*/
|
__IO uint32_t BAUDR; /*!< SPI²¨ÌØÂÊÑ¡Ôñ¼Ä´æÆ÷, offset:0x14*/
|
__IO uint32_t TXFTLR; /*!< SPI·¢ËÍFIFOãÐÖµÉèÖüĴæÆ÷, offset:0x18*/
|
__IO uint32_t RXFTLR; /*!< SPI½ÓÊÕFIFOãÐÖµÉèÖüĴæÆ÷, offset:0x1C*/
|
__I uint32_t TXFLR; /*!< SPI·¢ËÍFIFOãÐÖµ¼Ä´æÆ÷, offset:0x20*/
|
__I uint32_t RXFLR; /*!< SPI½ÓÊÕFIFOãÐÖµ¼Ä´æÆ÷, offset:0x24*/
|
__I uint32_t SR; /*!< SPI״̬¼Ä´æÆ÷, offset:0x28*/
|
__IO uint32_t IMR; /*!< SPIÖжÏÆÁ±Î¼Ä´æÆ÷, offset:0x2C*/
|
__I uint32_t ISR; /*!< SPIÖжÏ״̬¼Ä´æÆ÷, offset:0x30*/
|
__I uint32_t RISR; /*!< SPIÔʼÖжÏ״̬¼Ä´æÆ÷, offset:0x34*/
|
__I uint32_t TXOICR; /*!< SPI·¢ËÍFIFOÒç³öÖжÏÇåÁã¼Ä´æÆ÷, offset:0x38*/
|
__I uint32_t RXOICR; /*!< SPI½ÓÊÕFIFOÒç³öÖжÏÇåÁã¼Ä´æÆ÷, offset:0x3C*/
|
__I uint32_t RXUICR; /*!< SPI½ÓÊÕFIFOÏÂÒçÖжÏÇåÁã¼Ä´æÆ÷, offset:0x40*/
|
uint32_t RESERVED_1[1];
|
__I uint32_t ICR; /*!< SPIÖжÏÇåÁã¼Ä´æÆ÷, offset:0x48*/
|
__IO uint32_t DMACR; /*!< SPI DMA¿ØÖƼĴæÆ÷, offset:0x4C*/
|
__IO uint32_t DMATDLR; /*!< SPI DMA·¢ËÍÊý¾Ýˮƽ¼Ä´æÆ÷, offset:0x50*/
|
__IO uint32_t DMARDLR; /*!< SPI DMA½ÓÊÕÊý¾Ýˮƽ¼Ä´æÆ÷, offset:0x54*/
|
uint32_t RESERVED_2[1];
|
uint32_t RESERVED_3[1];
|
__IO uint32_t DR[36]; /*!< SPIÊý¾Ý¼Ä´æÆ÷, array offset: 0x60, array step: 0x4*/\
|
__IO uint32_t DLY; /*!< SPIÊý¾ÝÑÓ³Ù²ÉÑù¼Ä´æÆ÷, offset:0xF0*/
|
uint32_t RESERVED_4[1];
|
uint32_t RESERVED_5[1];
|
uint32_t RESERVED_6[1];
|
__IO uint32_t MODE; /*!< SPIģʽѡÔñ¼Ä´æÆ÷, array offset: 0x100 */
|
} SPI_Type;
|
//} SPI_Type, *SPI_MemMapPtr;
|
extern SPI_Type* SPI0;
|
extern SPI_Type* SPI1;
|
/** @addtogroup XL6600_StdPeriph_Driver
|
* @{
|
*/
|
|
/** @addtogroup SPI
|
* @{
|
*/
|
|
/* Exported types ------------------------------------------------------------*/
|
|
/**
|
* @brief SPIÖ÷»ú³õʼ»¯½á¹¹Ìå
|
*/
|
typedef struct
|
{
|
uint32_t SPI_SourceClk; /*!< ʱÖÓÔ´ */
|
uint32_t SPI_BAUDR; /*!< ²¨ÌØÂÊÑ¡Ôñ */
|
uint32_t SPI_SRL; /*!< ÒÆλ¼Ä´æÆ÷Ñ»· */
|
uint32_t SPI_TMOD; /*!< ´«Êäģʽ */
|
uint32_t SPI_SCPOL; /*!< ´®ÐÐʱÖÓ¼«ÐÔ */
|
uint32_t SPI_SCPH; /*!< ´®ÐÐʱÖÓÏàλ */
|
uint32_t SPI_DFS; /*!< Êý¾ÝÖ¡´óС */
|
uint32_t SPI_NDF; /*!< Êý¾ÝÖ¡ÊýÁ¿ */
|
uint32_t SPI_TFT; /*!< ·¢ËÍFIFOãÐÖµ */
|
uint32_t SPI_RFT; /*!< ½ÓÊÕFIFOãÐÖµ */
|
}SPI_MsterInitTypeDef, *SPI_MsterInitConfigPtr;
|
|
/**
|
* @brief SPI´Ó»ú³õʼ»¯½á¹¹Ìå
|
*/
|
typedef struct
|
{
|
FunctionalState SPI_SLVOE; /*!< ´Ó»úÊä³öʹÄÜ */
|
uint32_t SPI_SRL; /*!< ÒÆλ¼Ä´æÆ÷Ñ»· */
|
uint32_t SPI_TMOD; /*!< ´«Êäģʽ */
|
uint32_t SPI_SCPOL; /*!< ´®ÐÐʱÖÓ¼«ÐÔ */
|
uint32_t SPI_SCPH; /*!< ´®ÐÐʱÖÓÏàλ */
|
uint32_t SPI_DFS; /*!< Êý¾ÝÖ¡´óС */
|
uint32_t SPI_TFT; /*!< ·¢ËÍFIFOãÐÖµ */
|
uint32_t SPI_RFT; /*!< ½ÓÊÕFIFOãÐÖµ */
|
}SPI_SlaveInitTypeDef, *SPI_SlaveInitConfigPtr;
|
|
/* Exported constants --------------------------------------------------------*/
|
|
|
/** @defgroup SPI_Exported_Constants SPIÄ£¿éʹÓòÎÊý¶¨Òå
|
* @{
|
*/
|
|
/**
|
* @defgroup SPI_Work_Mode SPI¹¤×÷ģʽ
|
* @brief ʱÖÓÔ´Ñ¡Ôñ
|
* @{
|
*/
|
#define SPI_SRL_NORMAL ((uint16_t)0x0000) /*!< Õý³£Ä£Ê½¹¤×÷ */
|
#define SPI_SRL_TEST ((uint16_t)0x0800) /*!< ²âÊÔģʽ¹¤×÷ */
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup SPI_Transfer_Mode SPI´«Êäģʽ
|
* @{
|
*/
|
#define SPI_TransmitAndReceive ((uint16_t)0x0000) /*!< ·¢ËͺͽÓÊÕ */
|
#define SPI_TransmitOnly ((uint16_t)0x0100) /*!< ½ö·¢ËÍ */
|
#define SPI_ReceiveOnly ((uint16_t)0x0200) /*!< ½ö½ÓÊÕ */
|
#define SPI_EEPROMRead ((uint16_t)0x0300) /*!< EEPROM¶ÁÈ¡ */
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup SPI_Serial_Clock_Polarity SPIʱÖÓ¼«ÐÔ
|
* @{
|
*/
|
#define SPI_SCPOL_Low ((uint16_t)0x0000) /*!< SPIʱÖÓ¼«ÐÔΪµÍ */
|
#define SPI_SCPOL_High ((uint16_t)0x0080) /*!< SPIʱÖÓ¼«ÐÔλ¸ß */
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup SPI Serial Clock Phase
|
* @brief ʱÖÓÔ´Ñ¡Ôñ
|
* @{
|
*/
|
#define SPI_SCPH_Middle ((uint16_t)0x0000) /*!< ´®ÐÐʱÖÓÔÚµÚÒ»¸öÊý¾ÝλµÄÖмäÇл» */
|
#define SPI_SCPH_Start ((uint16_t)0x0040) /*!< ´®ÐÐʱÖÓÔÚµÚÒ»¸öÊý¾Ýλ¿ªÊ¼Ê±Çл» */
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup SPI_Data_Lenght SPIÊý¾Ý³¤¶È
|
* @{
|
*/
|
#define SPI_DataSize_4b ((uint16_t)0x0003) /*!< 4¨Dλ´®ÐÐÊý¾Ý´«Êä */
|
#define SPI_DataSize_5b ((uint16_t)0x0004) /*!< 5¨Dλ´®ÐÐÊý¾Ý´«Êä */
|
#define SPI_DataSize_6b ((uint16_t)0x0005) /*!< 6¨Dλ´®ÐÐÊý¾Ý´«Êä */
|
#define SPI_DataSize_7b ((uint16_t)0x0006) /*!< 7¨Dλ´®ÐÐÊý¾Ý´«Êä */
|
#define SPI_DataSize_8b ((uint16_t)0x0007) /*!< 8¨Dλ´®ÐÐÊý¾Ý´«Êä */
|
#define SPI_DataSize_9b ((uint16_t)0x0008) /*!< 9¨Dλ´®ÐÐÊý¾Ý´«Êä */
|
#define SPI_DataSize_10b ((uint16_t)0x0009) /*!< 10¨Dλ´®ÐÐÊý¾Ý´«Êä */
|
#define SPI_DataSize_11b ((uint16_t)0x000A) /*!< 11¨Dλ´®ÐÐÊý¾Ý´«Êä */
|
#define SPI_DataSize_12b ((uint16_t)0x000B) /*!< 12¨Dλ´®ÐÐÊý¾Ý´«Êä */
|
#define SPI_DataSize_13b ((uint16_t)0x000C) /*!< 13¨Dλ´®ÐÐÊý¾Ý´«Êä */
|
#define SPI_DataSize_14b ((uint16_t)0x000D) /*!< 14¨Dλ´®ÐÐÊý¾Ý´«Êä */
|
#define SPI_DataSize_15b ((uint16_t)0x000E) /*!< 15¨Dλ´®ÐÐÊý¾Ý´«Êä */
|
#define SPI_DataSize_16b ((uint16_t)0x000F) /*!< 16¨Dλ´®ÐÐÊý¾Ý´«Êä */
|
/**
|
* @}
|
*/
|
|
/**
|
* @brief SPI_Mode SPIģʽ
|
* @{
|
*/
|
typedef enum
|
{
|
SPI_MODE_MASTER = 0x00, /*!< Ö÷»úģʽ */
|
SPI_MODE_SLAVE = 0x01 /*!< ´Ó»úģʽ */
|
|
}SPI_MODETypeDef;
|
/**
|
* @}
|
*/
|
|
/**
|
* @brief SPI_Data_Pack SPI´«Êä°üÀàÐÍ
|
* @{
|
*/
|
typedef enum
|
{
|
SPI_PACK_CS_LOW = 0x00, /*!< ƬѡΪµÍ */
|
SPI_PACK_CS_HIGHT = 0x01 /*!< ƬѡΪ¸ß */
|
|
}SPI_PACKCSTypeDef;
|
/**
|
* @}
|
*/
|
|
/**
|
* @brief SPI TxRx_FIFO_Level SPI·¢ËÍ/½ÓÊÕFIFOÉî¶È
|
* @{
|
*/
|
typedef enum
|
{
|
SPI_TransmitFIFOLevel = 0x00, /*!< ·¢ËÍFIFOÓÐЧÊý¾Ý¸öÊý */
|
SPI_ReceiveFIFOLevel = 0x01 /*!< ½ÓÊÕFIFOÓÐЧÊý¾Ý¸öÊý */
|
|
}SPI_TXRXFIFOLevelDef;
|
/**
|
* @}
|
*/
|
|
/**
|
* @brief SPI_Status SPI״̬
|
* @{
|
*/
|
typedef enum
|
{
|
SPI_SPIBusyFlagStatus = 0, /*!< SPI·±Ã¦±ê־λ */
|
SPI_TransmitFIFONotFullStatus, /*!< ·¢ËÍFIFOδÂú */
|
SPI_TransmitFIFOEmptyStatus, /*!< ·¢ËÍFIFOΪ¿Õ */
|
SPI_ReceiveFIFONotEmptyStatus, /*!< ½ÓÊÕFIFO²»Îª¿Õ */
|
SPI_ReceiveFIFOFullStatus, /*!< ½ÓÊÕFIFOÒÑÂú */
|
SPI_TransmissionErrorStatus, /*!< Êý¾Ý·¢ËÍ´íÎó£¬Ö»ÓÐSPIΪ´Ó»úʱ²ÅÄÜʹÓô˹¦ÄÜ */
|
SPI_DataCollisionErrorStatus /*!< Êý¾Ý³åÍ»´íÎó£¬Ö»ÓÐSPIΪÖ÷»úʱ²ÅÓд˹¦ÄÜ*/
|
|
}SPI_StatusTypeDef;
|
/**
|
* @}
|
*/
|
|
/**
|
* @brief SPI_Interrupt_Status SPIÖжÏ״̬
|
* @{
|
*/
|
typedef enum
|
{
|
SPI_TransmitFIFOEmptyIT = 0, /*!< ·¢ËÍFIFOÒÑ¿ÕµÄÖжÏÑÚÂë */
|
SPI_TransmitFIFOOverflowIT, /*!< ·¢ËÍFIFOÒç³öµÄÖжÏÑÚÂë */
|
SPI_ReceiveFIFOUnderflowIT, /*!< ½ÓÊÕFIFOÏÂÒçµÄÖжÏÑÚÂë */
|
SPI_ReceiveFIFOOverflowIT, /*!< ½ÓÊÕFIFOÒç³öµÄÖжÏÑÚÂë */
|
SPI_ReceiveFIFOFullIT , /*!< ½ÓÊÕFIFOÒÑÂúµÄÖжÏÑÚÂë */
|
SPI_ALLIT = 0xFu /*!< ËùÓÐÑÚÂë */
|
}SPI_InterruptTypeDef;
|
/**
|
* @}
|
*/
|
|
/**
|
* @brief SPI_Interrupt_Mask SPIÖжÏÆÁ±Î
|
* @{
|
*/
|
typedef enum
|
{
|
SPI_TransmitFIFOEmptyITStatus = 0, /*!< ·¢ËÍFIFOÒÑ¿ÕµÄÖжÏ״̬ */
|
SPI_TransmitFIFOOverflowITStatus, /*!< ·¢ËÍFIFOÒç³öµÄÖжÏ״̬ */
|
SPI_ReceiveFIFOUnderflowITStatus, /*!< ½ÓÊÕFIFOÏÂÒçµÄÖжÏ״̬ */
|
SPI_ReceiveFIFOOverflowITStatus, /*!< ½ÓÊÕFIFOÒç³öµÄÖжÏ״̬ */
|
SPI_ReceiveFIFOFullITStatus /*!< ½ÓÊÕFIFOÒÑÂúµÄÖжÏ״̬ */
|
|
}SPI_ITStatusMaskedDef;
|
/**
|
* @}
|
*/
|
|
/**
|
* @brief SPI_Raw_Interrupt_Status SPIÖжÏǰ״̬
|
* @{
|
*/
|
typedef enum
|
{
|
SPI_TransmitFIFOEmptyRawITStatus = 0, /*!< ·¢ËÍFIFOÔʼÖжÏΪ¿Õ״̬ */
|
SPI_TransmitFIFOOverflowRawITStatus, /*!< ·¢ËÍFIFOÔʼ״̬Òç³ö״̬ */
|
SPI_ReceiveFIFOUnderflowRawITStatus, /*!< ½ÓÊÕFIFOÔʼÖжÏÏÂÒç״̬ */
|
SPI_ReceiveFIFOOverflowRawITStatus, /*!< ½ÓÊÕFIFOÔʼÖжÏÒç³ö״̬ */
|
SPI_ReceiveFIFOFullRawITStatus /*!< ½ÓÊÕFIFOÔʼÖжÏÒÑÂú״̬ */
|
|
}SPI_RawITStatusTypeDef;
|
/**
|
* @}
|
*/
|
|
/**
|
* @brief SPI_Clear_Interrupt SPIÇå³ýÖжϱêÖ¾
|
* @{
|
*/
|
typedef enum
|
{
|
SPI_TransmitFIFOOverflowITClear = 0, /*!< Çå¿Õ·¢ËÍFIFOÒç³öÖжϼĴæÆ÷ */
|
SPI_ReceiveFIFOOverflowITClear, /*!< Çå¿Õ½ÓÊÕFIFOÒç³öÖжϼĴæÆ÷ */
|
SPI_ReceiveFIFOUnderflowITClear, /*!< Çå¿Õ½ÓÊÕFIFOÏÂÒçÖжϼĴæÆ÷ */
|
SPI_ALLITClear /*!< Çå¿ÕËùÓÐÖжÏ״̬ */
|
|
}SPI_InterruptClearDef;
|
/**
|
* @}
|
*/
|
|
|
/**
|
* @}
|
*/
|
|
/* Exported macro ------------------------------------------------------------*/
|
/* Exported functions --------------------------------------------------------*/
|
void SPI_DeInit(SPI_Type *SPIx);
|
void SPI_SetMode(SPI_Type *SPIx,SPI_MODETypeDef SPI_MODEType);
|
void SPI_SetPackCS(SPI_Type *SPIx,SPI_PACKCSTypeDef SPI_PACKCSType);
|
void SPI_MasterInit(SPI_Type* SPIx, const SPI_MsterInitTypeDef *SPI_MasterInitStruct);
|
void SPI_SlaveInit(SPI_Type* SPIx,const SPI_SlaveInitTypeDef *SPI_SlaveInitStruct);
|
void SPI_EnableCmd(SPI_Type *SPIx,FunctionalState NewState);
|
void SPI_SlaveEnableCmd(SPI_Type *SPIx,FunctionalState NewState);
|
void SPI_SendData(SPI_Type *SPIx,uint16_t Data);
|
uint16_t SPI_ReceiveData(const SPI_Type *SPIx);
|
uint8_t SPI_GetFIFOLevel(const SPI_Type *SPIx,SPI_TXRXFIFOLevelDef FIFOLevelDef);
|
uint8_t SPI_GetStatus(const SPI_Type *SPIx,SPI_StatusTypeDef SPI_StatusType);
|
void SPI_InterruptEn(SPI_Type *SPIx, SPI_InterruptTypeDef SPI_Interrupt, FunctionalState NewState);
|
uint8_t SPI_ClearInterrupt(const SPI_Type *SPIx, SPI_InterruptClearDef SPI_Interrupt2Clear);
|
uint8_t SPI_GetIntMaskedStatus(const SPI_Type *SPIx,SPI_ITStatusMaskedDef SPI_IntStatusType);
|
uint8_t SPI_GetRawIntStatus(const SPI_Type *SPIx,SPI_RawITStatusTypeDef SPI_RawIntStatusType);
|
void SPI_SetDMATxDataLenght(SPI_Type *SPIx,uint8_t lenght);
|
void SPI_SetDMARxDataLenght(SPI_Type *SPIx,uint8_t lenght);
|
void SPI_DMATxEnableCmd(SPI_Type *SPIx,FunctionalState NewState);
|
void SPI_DMARxEnableCmd(SPI_Type *SPIx,FunctionalState NewState);
|
void SPI_DelaySampling(SPI_Type *SPIx,uint32_t nclock);
|
#ifdef __cplusplus
|
}
|
#endif
|
|
#endif /*__XL_SPI_H */
|
/**
|
* @}
|
*/
|
|
/**
|
* @}
|
*/
|
