/**
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******************************************************************************
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* @file xl_sim.h
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* @author software group
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* @brief This file contains all the functions prototypes for the SIM
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* firmware library.
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******************************************************************************
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* @attention
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*
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* 2019 by Chipways Communications,Inc. All Rights Reserved.
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* This software is supplied under the terms of a license
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* agreement or non-disclosure agreement with Chipways.
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* Passing on and copying of this document,and communication
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* of its contents is not permitted without prior written
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* authorization.
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*
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* <h2><center>© COPYRIGHT 2019 Chipways</center></h2>
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __XL_SIM_H_
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#define __XL_SIM_H_
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#ifdef __cplusplus
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extern "C"{
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#endif
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/* Includes ---------------------------------------------------------------*/
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#include "xl6600.h"
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/* Register define ------------------------------------------------------------*/
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/* SRSID Bit Fields */
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#define SIM_SRSID_ECCERR_MASK 0x00000001u
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#define SIM_SRSID_ECCERR_SHIFT 0
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#define SIM_SRSID_LVD_MASK 0x00000002u
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#define SIM_SRSID_LVD_SHIFT 1
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#define SIM_SRSID_WDOG_MASK 0x00000020u
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#define SIM_SRSID_WDOG_SHIFT 5
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#define SIM_SRSID_PIN_MASK 0x00000040u
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#define SIM_SRSID_PIN_SHIFT 6
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#define SIM_SRSID_POR_MASK 0x00000080u
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#define SIM_SRSID_POR_SHIFT 7
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#define SIM_SRSID_SW_MASK 0x00000400u
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#define SIM_SRSID_SW_SHIFT 10
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#define SIM_SRSID_PINID_MASK 0x000F0000u
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#define SIM_SRSID_PINID_SHIFT 16
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/* SOPT0 Bit Fields */
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#define SIM_SOPT0_NMIE_MASK 0x00000002u
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#define SIM_SOPT0_NMIE_SHIFT 1
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#define SIM_SOPT0_RSTPE_MASK 0x00000004u
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#define SIM_SOPT0_RSTPE_SHIFT 2
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#define SIM_SOPT0_SWDE_MASK 0x00000008u
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#define SIM_SOPT0_SWDE_SHIFT 3
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#define SIM_SOPT0_ACTRG_MASK 0x00000020u
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#define SIM_SOPT0_ACTRG_SHIFT 5
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#define SIM_SOPT0_RXDFE_MASK 0x00000300u
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#define SIM_SOPT0_RXDFE_SHIFT 8
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#define SIM_SOPT0_RTCC_MASK 0x00000400u
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#define SIM_SOPT0_RTCC_SHIFT 10
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#define SIM_SOPT0_ACIC_MASK 0x00000800u
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#define SIM_SOPT0_ACIC_SHIFT 11
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#define SIM_SOPT0_RXDCE_MASK 0x00001000u
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#define SIM_SOPT0_RXDCE_SHIFT 12
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#define SIM_SOPT0_FTMSYNC_MASK 0x00004000u
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#define SIM_SOPT0_FTMSYNC_SHIFT 14
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#define SIM_SOPT0_TXDME_MASK 0x00008000u
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#define SIM_SOPT0_TXDME_SHIFT 15
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#define SIM_SOPT0_BUSREF_MASK 0x00070000u
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#define SIM_SOPT0_BUSREF_SHIFT 16
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#define SIM_SOPT0_CLKOE_MASK 0x00080000u
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#define SIM_SOPT0_CLKOE_SHIFT 19
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#define SIM_SOPT0_DLYACT_MASK 0x00800000u
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#define SIM_SOPT0_DLYACT_SHIFT 23
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#define SIM_SOPT0_DELAY_MASK 0xFF000000u
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#define SIM_SOPT0_DELAY_SHIFT 24
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/* SOPT1 Bit Fields */
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#define SIM_SOPT1_ACPWTS_MASK 0x8u
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#define SIM_SOPT1_ACPWTS_SHIFT 3
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#define SIM_SOPT1_UARTPWTS_MASK 0x60u
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#define SIM_SOPT1_UARTPWTS_SHIFT 5
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#define SIM_SOPT1_ADHWT_MASK 0xF00u
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#define SIM_SOPT1_ADHWT_SHIFT 8
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/* PINSEL0 Bit Fields */
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#define SIM_PINSEL0_UART0PS_MASK 0x0000000Cu
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#define SIM_PINSEL0_UART0PS_SHIFT 2
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#define SIM_PINSEL0_FTM0PS0_MASK 0x00000030u
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#define SIM_PINSEL0_FTM0PS0_SHIFT 4
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#define SIM_PINSEL0_FTM0PS1_MASK 0x000000C0u
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#define SIM_PINSEL0_FTM0PS1_SHIFT 6
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#define SIM_PINSEL0_FTM1PS0_MASK 0x00000300u
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#define SIM_PINSEL0_FTM1PS0_SHIFT 8
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#define SIM_PINSEL0_FTM1PS1_MASK 0x00000C00u
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#define SIM_PINSEL0_FTM1PS1_SHIFT 10
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#define SIM_PINSEL0_FTMFLT2PS_MASK 0x00003000u
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#define SIM_PINSEL0_FTMFLT2PS_SHIFT 12
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#define SIM_PINSEL0_FTMFLT1PS_MASK 0x0000C000u
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#define SIM_PINSEL0_FTMFLT1PS_SHIFT 14
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#define SIM_PINSEL0_BUSOUTPS_MASK 0x00030000u
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#define SIM_PINSEL0_BUSOUTPS_SHIFT 16
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#define SIM_PINSEL0_TCLK2PS_MASK 0x000C0000u
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#define SIM_PINSEL0_TCLK2PS_SHIFT 18
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#define SIM_PINSEL0_TCLK1PS_MASK 0x00300000u
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#define SIM_PINSEL0_TCLK1PS_SHIFT 20
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#define SIM_PINSEL0_TCLK0PS_MASK 0x00C00000u
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#define SIM_PINSEL0_TCLK0PS_SHIFT 22
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#define SIM_PINSEL0_FTM0CLKPS_MASK 0x03000000u
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#define SIM_PINSEL0_FTM0CLKPS_SHIFT 24
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#define SIM_PINSEL0_FTM1CLKPS_MASK 0x0C000000u
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#define SIM_PINSEL0_FTM1CLKPS_SHIFT 26
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#define SIM_PINSEL0_FTM2CLKPS_MASK 0x30000000u
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#define SIM_PINSEL0_FTM2CLKPS_SHIFT 28
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#define SIM_PINSEL0_PWTCLKPS_MASK 0xC0000000u
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#define SIM_PINSEL0_PWTCLKPS_SHIFT 30
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/* PINSEL1 Bit Fields */
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#define SIM_PINSEL1_FTM2PS0_MASK 0x00000003u
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#define SIM_PINSEL1_FTM2PS0_SHIFT 0
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#define SIM_PINSEL1_FTM2PS1_MASK 0x0000000Cu
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#define SIM_PINSEL1_FTM2PS1_SHIFT 2
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#define SIM_PINSEL1_FTM2PS2_MASK 0x00000030u
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#define SIM_PINSEL1_FTM2PS2_SHIFT 4
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#define SIM_PINSEL1_FTM2PS3_MASK 0x000000C0u
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#define SIM_PINSEL1_FTM2PS3_SHIFT 6
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#define SIM_PINSEL1_FTM2PS4_MASK 0x00000100u
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#define SIM_PINSEL1_FTM2PS4_SHIFT 8
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#define SIM_PINSEL1_FTM2PS5_MASK 0x00000200u
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#define SIM_PINSEL1_FTM2PS5_SHIFT 9
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#define SIM_PINSEL1_I2C1PS_MASK 0x00000400u
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#define SIM_PINSEL1_I2C1PS_SHIFT 10
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#define SIM_PINSEL1_SPI1PS_MASK 0x00000800u
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#define SIM_PINSEL1_SPI1PS_SHIFT 11
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#define SIM_PINSEL1_UART1PS_MASK 0x00001000u
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#define SIM_PINSEL1_UART1PS_SHIFT 12
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#define SIM_PINSEL1_UART2PS_MASK 0x00002000u
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#define SIM_PINSEL1_UART2PS_SHIFT 13
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#define SIM_PINSEL1_PWTIN0PS_MASK 0x00004000u
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#define SIM_PINSEL1_PWTIN0PS_SHIFT 14
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#define SIM_PINSEL1_PWTIN1PS_MASK 0x00008000u
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#define SIM_PINSEL1_PWTIN1PS_SHIFT 15
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#define SIM_PINSEL1_SPI0PS_MASK 0x00010000u
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#define SIM_PINSEL1_SPI0PS_SHIFT 16
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#define SIM_PINSEL1_EWMPS_MASK 0x00060000u
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#define SIM_PINSEL1_EWMPS_SHIFT 17
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#define SIM_PINSEL1_IRQPS_MASK 0x00380000u
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#define SIM_PINSEL1_IRQPS_SHIFT 19
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#define SIM_PINSEL1_ACMP1PS_MASK 0x00400000u
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#define SIM_PINSEL1_ACMP1PS_SHIFT 22
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#define SIM_PINSEL1_RTCPS_MASK 0x00800000u
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#define SIM_PINSEL1_RTCPS_SHIFT 23
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#define SIM_PINSEL1_I2C0PS_MASK 0x01000000u
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#define SIM_PINSEL1_I2C0PS_SHIFT 24
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#define SIM_PINSEL1_FTM0PS2_MASK 0x02000000u
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#define SIM_PINSEL1_FTM0PS2_SHIFT 25
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#define SIM_PINSEL1_FTM0PS3_MASK 0x04000000u
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#define SIM_PINSEL1_FTM0PS3_SHIFT 26
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#define SIM_PINSEL1_FTM1PS2_MASK 0x08000000u
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#define SIM_PINSEL1_FTM1PS2_SHIFT 27
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#define SIM_PINSEL1_FTM1PS3_MASK 0x10000000u
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#define SIM_PINSEL1_FTM1PS3_SHIFT 28
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#define SIM_PINSEL1_FTM2PS6_MASK 0x20000000u
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#define SIM_PINSEL1_FTM2PS6_SHIFT 29
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#define SIM_PINSEL1_FTM2PS7_MASK 0x40000000u
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#define SIM_PINSEL1_FTM2PS7_SHIFT 30
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/* SCGC Bit Fields */
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#define SIM_SCGC_RTC_MASK 0x00000001u
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#define SIM_SCGC_RTC_SHIFT 0
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#define SIM_SCGC_PIT_MASK 0x00000002u
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#define SIM_SCGC_PIT_SHIFT 1
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#define SIM_SCGC_EWM_MASK 0x00000004u
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#define SIM_SCGC_EWM_SHIFT 2
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#define SIM_SCGC_PWT_MASK 0x00000010u
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#define SIM_SCGC_PWT_SHIFT 4
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#define SIM_SCGC_FTM0_MASK 0x00000020u
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#define SIM_SCGC_FTM0_SHIFT 5
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#define SIM_SCGC_FTM1_MASK 0x00000040u
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#define SIM_SCGC_FTM1_SHIFT 6
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#define SIM_SCGC_FTM2_MASK 0x00000080u
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#define SIM_SCGC_FTM2_SHIFT 7
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#define SIM_SCGC_CLMA_MASK 0x00000100u
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#define SIM_SCGC_CLMA_SHIFT 8
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#define SIM_SCGC_CLMB_MASK 0x00000200u
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#define SIM_SCGC_CLMB_SHIFT 9
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#define SIM_SCGC_CRC_MASK 0x00000400u
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#define SIM_SCGC_CRC_SHIFT 10
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#define SIM_SCGC_WDG_MASK 0x00000800u
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#define SIM_SCGC_WDG_SHIFT 11
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#define SIM_SCGC_MCAN_MASK 0x00004000u
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#define SIM_SCGC_MCAN_SHIFT 14
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#define SIM_SCGC_I2C0_MASK 0x00010000u
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#define SIM_SCGC_I2C0_SHIFT 16
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#define SIM_SCGC_I2C1_MASK 0x00020000u
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#define SIM_SCGC_I2C1_SHIFT 17
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#define SIM_SCGC_SPI0_MASK 0x00040000u
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#define SIM_SCGC_SPI0_SHIFT 18
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#define SIM_SCGC_SPI1_MASK 0x00080000u
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#define SIM_SCGC_SPI1_SHIFT 19
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#define SIM_SCGC_UART0_MASK 0x00100000u
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#define SIM_SCGC_UART0_SHIFT 20
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#define SIM_SCGC_UART1_MASK 0x00200000u
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#define SIM_SCGC_UART1_SHIFT 21
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#define SIM_SCGC_UART2_MASK 0x00400000u
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#define SIM_SCGC_UART2_SHIFT 22
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#define SIM_SCGC_KBI0_MASK 0x01000000u
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#define SIM_SCGC_KBI0_SHIFT 24
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#define SIM_SCGC_KBI1_MASK 0x02000000u
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#define SIM_SCGC_KBI1_SHIFT 25
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#define SIM_SCGC_IRQ_MASK 0x08000000u
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#define SIM_SCGC_IRQ_SHIFT 27
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#define SIM_SCGC_DMA_MASK 0x10000000u
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#define SIM_SCGC_DMA_SHIFT 28
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#define SIM_SCGC_ADC_MASK 0x20000000u
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#define SIM_SCGC_ADC_SHIFT 29
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#define SIM_SCGC_ACMP0_MASK 0x40000000u
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#define SIM_SCGC_ACMP0_SHIFT 30
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#define SIM_SCGC_ACMP1_MASK 0x80000000u
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#define SIM_SCGC_ACMP1_SHIFT 31
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/* UUIDL Bit Fields */
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#define SIM_UUIDL_ID_MASK 0xFFFFFFFFu
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#define SIM_UUIDL_ID_SHIFT 0
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/* UUIDML Bit Fields */
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#define SIM_UUIDML_ID_MASK 0xFFFFFFFFu
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#define SIM_UUIDML_ID_SHIFT 0
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/* UUIDMH Bit Fields */
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#define SIM_UUIDMH_SS_MASK 0x0000000Fu
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#define SIM_UUIDMH_SS_SHIFT 0
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#define SIM_UUIDMH_FS_MASK 0x000000F0u
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#define SIM_UUIDMH_FS_SHIFT 4
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#define SIM_UUIDMH_VER_MASK 0x0000FF00u
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#define SIM_UUIDMH_VER_SHIFT 8
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#define SIM_UUIDMH_DEVID_MASK 0xFFFF0000u
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#define SIM_UUIDMH_DEVID_SHIFT 16
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/* CLKDIV Bit Fields */
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#define SIM_CLKDIV_OUTDIV1_MASK 0x000000FFu
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#define SIM_CLKDIV_OUTDIV1_SHIFT 0
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#define SIM_CLKDIV_OUTDIV2_MASK 0x0000FF00u
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#define SIM_CLKDIV_OUTDIV2_SHIFT 8
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#define SIM_CLKDIV_OUTDIV3_MASK 0x00FF0000u
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#define SIM_CLKDIV_OUTDIV3_SHIFT 16
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#define SIM_CLKDIV_OUTDIV4_MASK 0xFF000000u
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#define SIM_CLKDIV_OUTDIV4_SHIFT 24
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/* SCGC1 Bit Fields */
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#define SIM_SCGC1_FTM0F_MASK 0x00000001u
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#define SIM_SCGC1_FTM0F_SHIFT 0
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#define SIM_SCGC1_FTM1F_MASK 0x00000002u
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#define SIM_SCGC1_FTM1F_SHIFT 1
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#define SIM_SCGC1_FTM2F_MASK 0x00000004u
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#define SIM_SCGC1_FTM2F_SHIFT 2
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#define SIM_SCGC1_RTCOEC_MASK 0x00000020u
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#define SIM_SCGC1_RTCOEC_SHIFT 5
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#define SIM_SCGC1_ADCALTC_MASK 0x00000040u
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#define SIM_SCGC1_ADCALTC_SHIFT 6
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#define SIM_SCGC1_FTM0T_MASK 0x01000000u
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#define SIM_SCGC1_FTM0T_SHIFT 24
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#define SIM_SCGC1_FTM1T_MASK 0x02000000u
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#define SIM_SCGC1_FTM1T_SHIFT 25
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#define SIM_SCGC1_FTM2T_MASK 0x04000000u
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#define SIM_SCGC1_FTM2T_SHIFT 26
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#define SIM_SCGC1_WDOGLPO_MASK 0x8000000u
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#define SIM_SCGC1_WDOGLPO_SHIFT 27
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#define SIM_SCGC1_RTCLPOC_MASK 0x10000000u
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#define SIM_SCGC1_RTCLPOC_SHIFT 28
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#define SIM_SCGC1_FTM0FF_MASK 0x20000000u
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#define SIM_SCGC1_FTM0FF_SHIFT 29
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#define SIM_SCGC1_FTM1FF_MASK 0x40000000u
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#define SIM_SCGC1_FTM1FF_SHIFT 30
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#define SIM_SCGC1_FTM2FF_MASK 0x80000000u
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#define SIM_SCGC1_FTM2FF_SHIFT 31
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/* LP Bit Fields */
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#define SIM_LP_FLASHPOFF_MASK 0x00000004u
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#define SIM_LP_FLASHPOFF_SHIFT 2
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#define SIM_LP_FLASHPOFFST_MASK 0x00000008u
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#define SIM_LP_FLASHPOFFST_SHIFT 3
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#define SIM_LP_SRAM1POFF_MASK 0x00000020u
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#define SIM_LP_SRAM1POFF_SHIFT 5
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#define SIM_LP_SRAM2POFF_MASK 0x00000040u
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#define SIM_LP_SRAM2POFF_SHIFT 6
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#define SIM_LP_SRAM3POFF_MASK 0x00000080u
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#define SIM_LP_SRAM3POFF_SHIFT 7
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#define SIM_LP_SRAM1POFFST_MASK 0x00000200u
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#define SIM_LP_SRAM1POFFST_SHIFT 9
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#define SIM_LP_SRAM2POFFST_MASK 0x00000400u
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#define SIM_LP_SRAM2POFFST_SHIFT 10
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#define SIM_LP_SRAM3POFFST_MASK 0x00000800u
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#define SIM_LP_SRAM3POFFST_SHIFT 11
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#define SIM_LP_FLASHPON_MASK 0x00001000u
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#define SIM_LP_FLASHPON_SHIFT 12
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#define SIM_LP_SRAMPON_MASK 0x00002000u
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#define SIM_LP_SRAMPON_SHIFT 13
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#define SIM_LP_WEN_MASK 0xFFFF0000u
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#define SIM_LP_WEN_SHIFT 16
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/* WAIT Bit Fields */
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#define SIM_WAIT_CLKWAIT_MASK 0x0000FFFFu
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#define SIM_WAIT_CLKWAIT_SHIFT 0
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#define SIM_WAIT_DIV1US_MASK 0x00FF0000u
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#define SIM_WAIT_DIV1US_SHIFT 16
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/** SIM - Register Layout Typedef */
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typedef struct {
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__IO uint32_t SRSID; /**< ϵͳ¸´Î»×´Ì¬ºÍID¼Ä´æÆ÷, offset: 0x0 */
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__IO uint32_t SOPT0; /**< ϵͳѡÏî¼Ä´æÆ÷0, offset: 0x4 */
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__IO uint32_t SOPT1; /**< ϵͳѡÏî¼Ä´æÆ÷, offset: 0x8 */
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__IO uint32_t PINSEL0; /**< Òý½ÅÑ¡Ôñ¼Ä´æÆ÷0, offset: 0xC */
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__IO uint32_t PINSEL1; /**< Òý½ÅÑ¡Ôñ¼Ä´æÆ÷1, offset: 0x10 */
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__IO uint32_t SCGC; /**< ϵͳʱÖÓѡͨ¿ØÖƼĴæÆ÷, offset: 0x14 */
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__I uint32_t UUIDL; /**< ͨÓÃΨһ±êʶ·ûµÍλ¼Ä´æÆ÷, offset: 0x18 */
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__I uint32_t UUIDML; /**< ͨÓÃΨһ±êʶ·ûÖеÍλ¼Ä´æÆ÷, offset: 0x1C */
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__I uint32_t UUIDMH; /**< ͨÓÃΨһ±êʶ·ûÖиßλ¼Ä´æÆ÷, offset: 0x20 */
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__IO uint32_t CLKDIV; /**< ʱÖÓ·ÖƵÆ÷¼Ä´æÆ÷, offset: 0x24 */
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__IO uint32_t SCGC1; /**< ϵͳʱÖÓѡͨ¿ØÖƼĴæÆ÷1, offset: 0x28 */
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uint32_t RESERVED_0[1];
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__IO uint32_t LP; /**< ϵͳ¹¦ºÄ¿ØÖƼĴæÆ÷, offset: 0x30 */
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__IO uint32_t WAIT; /**< ϵͳʱÖÓÎȶ¨µÈ´ý¼Ä´æÆ÷, offset: 0x34 */
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} SIM_Type;
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extern SIM_Type* SIM;
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/** @addtogroup XL6600_StdPeriph_Driver
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* @{
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*/
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/** @addtogroup SIM
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup SIM_Exported_Constants SIMÄ£¿éʹÓòÎÊý¶¨Òå
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* @{
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*/
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/**
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* @defgroup System_Reset ϵͳ¸´Î»±êÖ¾
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* @{
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*/
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#define SIM_ECCERR_RESET SIM_SRSID_ECCERR_SHIFT
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#define SIM_LVD_RESET SIM_SRSID_LVD_SHIFT
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#define SIM_WDOG_RESET SIM_SRSID_WDOG_SHIFT
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#define SIM_PIN_RESET SIM_SRSID_PIN_SHIFT
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#define SIM_POR_RESET SIM_SRSID_POR_SHIFT
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#define SIM_SW_RESET SIM_SRSID_SW_SHIFT
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/**
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* @}
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*/
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/**
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* @defgroup FTM2_Delay_Trigger FTM2´¥·¢ÑÓ³Ù
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* @{
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*/
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#define ACMP0_OUTPUT_TRIGGER_FTM2 ((uint8_t)0x00)
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#define ACMP1_OUTPUT_TRIGGER_FTM2 ((uint8_t)0x01)
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/**
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* @}
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*/
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/**
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* @defgroup UART0_RxD_Filter UART_RxDÂ˲¨Æ÷Æ÷Ñ¡Ôñ
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* @{
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*/
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#define UART0_RXD0_FILTER_NONE ((uint8_t)0x00)
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#define UART0_RXD0_FILTER_ACMP0 ((uint8_t)0x01)
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#define UART0_RXD0_FILTER_ACMP1 ((uint8_t)0x02)
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/**
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* @}
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*/
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/**
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* @defgroup BUSCLK_Output_Div BUSCLKʱÖÓÊä³ö·ÖƵÆ÷
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* @{
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*/
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#define BUSCLOCK_OUTPUT_DIVIDE_1 ((uint8_t)0x00)
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#define BUSCLOCK_OUTPUT_DIVIDE_2 ((uint8_t)0x01)
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#define BUSCLOCK_OUTPUT_DIVIDE_4 ((uint8_t)0x02)
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#define BUSCLOCK_OUTPUT_DIVIDE_8 ((uint8_t)0x03)
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#define BUSCLOCK_OUTPUT_DIVIDE_16 ((uint8_t)0x04)
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#define BUSCLOCK_OUTPUT_DIVIDE_32 ((uint8_t)0x05)
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#define BUSCLOCK_OUTPUT_DIVIDE_64 ((uint8_t)0x06)
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#define BUSCLOCK_OUTPUT_DIVIDE_128 ((uint8_t)0x07)
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/**
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* @}
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*/
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/**
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* @defgroup PWTIN2_To_ACMP PWTÊäÈëÁ¬½Óµ½ACMPÊä³ö
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* @{
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*/
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#define PWTIN2_INPUT_ACMP1OUT ((uint8_t)0x00)
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#define PWTIN2_INPUT_ACMP0OUT ((uint8_t)0x01)
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/**
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* @}
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*/
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/**
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* @defgroup PWTIN3_To_UART PWTÊäÈëÁ¬½Óµ½UARTÊä³ö
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* @{
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*/
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#define PWTIN3_INPUT_UART0RX ((uint8_t)0x00)
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#define PWTIN3_INPUT_UART1RX ((uint8_t)0x01)
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#define PWTIN3_INPUT_UART2RX ((uint8_t)0x02)
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/**
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* @}
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*/
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/**
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* @defgroup ADC_Hardware_Trigger_Source ADCÓ²¼þ´¥·¢Ô´
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* @{
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*/
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#define ADC_HT_RTCOVERFLOW ((uint8_t)0x00)
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#define ADC_HT_FTM0CH0MAP ((uint8_t)0x01)
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#define ADC_HT_FTM2UPDATE ((uint8_t)0x02)
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#define ADC_HT_FTM2CH0MAP ((uint8_t)0x03)
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#define ADC_HT_PITCH0OVERFLOW ((uint8_t)0x04)
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#define ADC_HT_PITCH1OVERFLOW ((uint8_t)0x05)
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#define ADC_HT_ACMP0OUTPUT ((uint8_t)0x06)
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#define ADC_HT_ACMP1OUTPUT ((uint8_t)0x07)
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#define ADC_HT_FTM2CH1MAP ((uint8_t)0x08)
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#define ADC_HT_FTM2CH2MAP ((uint8_t)0x09)
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#define ADC_HT_FTM2CH3MAP ((uint8_t)0x0A)
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#define ADC_HT_FTM2CH4MAP ((uint8_t)0x0B)
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#define ADC_HT_FTM2CH5MAP ((uint8_t)0x0C)
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#define ADC_HT_FTM1CH0MAP ((uint8_t)0x0D)
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#define ADC_HT_FTM1CH1MAP ((uint8_t)0x0E)
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#define ADC_HT_FTM0CH1MAP ((uint8_t)0x0F)
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/**
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* @}
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*/
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/**
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* @defgroup UART0_PIN_SEL UART0¶Ë¿ÚÒý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define UART0_PS_PTB0_PTB1 ((uint8_t)0x00)
|
#define UART0_PS_PTA2_PTA3 ((uint8_t)0x01)
|
#define UART0_PS_PTC2_PTC3 ((uint8_t)0x02)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup FTM0PS0_PIN_SEL FTM0ͨµÀ0¶Ë¿ÚÒý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define FTM0CH0_PS_PTA0 ((uint8_t)0x00)
|
#define FTM0CH0_PS_PTB2 ((uint8_t)0x01)
|
#define FTM0CH0_PS_PTE5 ((uint8_t)0x02)
|
#define FTM0CH0_PS_PTF4 ((uint8_t)0x03)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup FTM0PS1_PIN_SEL FTM0ͨµÀ1¶Ë¿ÚÒý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define FTM0CH1_PS_PTA1 ((uint8_t)0x00)
|
#define FTM0CH1_PS_PTB3 ((uint8_t)0x01)
|
#define FTM0CH1_PS_PTE6 ((uint8_t)0x02)
|
#define FTM0CH1_PS_PTF5 ((uint8_t)0x03)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup FTM1PS0_PIN_SEL FTM1ͨµÀ0¶Ë¿ÚÒý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define FTM1CH0_PS_PTC4 ((uint8_t)0x00)
|
#define FTM1CH0_PS_PTH2 ((uint8_t)0x01)
|
#define FTM1CH0_PS_PTE5 ((uint8_t)0x02)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup FTM1PS1_PIN_SEL FTM1ͨµÀ1¶Ë¿ÚÒý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define FTM1CH1_PS_PTC5 ((uint8_t)0x00)
|
#define FTM1CH1_PS_PTE7 ((uint8_t)0x01)
|
#define FTM1CH1_PS_PTE6 ((uint8_t)0x02)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup FTM_FLT2_PIN_SEL FTM_FLT2¶Ë¿ÚÒý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define FTM_FLT2_PS_PTA7 ((uint8_t)0x00)
|
#define FTM_FLT2_PS_PTI1 ((uint8_t)0x01)
|
#define FTM_FLT2_PS_PTF7 ((uint8_t)0x02)
|
#define FTM_FLT2_PS_PTF6 ((uint8_t)0x03)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup FTM_FLT1_PIN_SEL FTM_FLT1¶Ë¿ÚÒý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define FTM_FLT1_PS_PTA6 ((uint8_t)0x00)
|
#define FTM_FLT1_PS_PTI1 ((uint8_t)0x01)
|
#define FTM_FLT1_PS_PTF7 ((uint8_t)0x02)
|
#define FTM_FLT1_PS_PTF6 ((uint8_t)0x03)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup BUSOUT_PIN_SEL BUSCLKÊä³ö¶Ë¿ÚÒý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define BUSOUT_PS_PTH2 ((uint8_t)0x00)
|
#define BUSOUT_PS_PTH6 ((uint8_t)0x01)
|
#define BUSOUT_PS_PTB5 ((uint8_t)0x02)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup TCLK2_PIN_SEL TCLK2¶Ë¿ÚÒý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define TCLK2_PS_PTE7 ((uint8_t)0x00)
|
#define TCLK2_PS_PTH7 ((uint8_t)0x01)
|
#define TCLK2_PS_PTD5 ((uint8_t)0x02)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup TCLK1_PIN_SEL TCLK1¶Ë¿ÚÒý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define TCLK1_PS_PTE0 ((uint8_t)0x00)
|
#define TCLK1_PS_PTH7 ((uint8_t)0x01)
|
#define TCLK1_PS_PTD5 ((uint8_t)0x02)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup TCLK0_PIN_SEL TCLK0¶Ë¿ÚÒý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define TCLK0_PS_PTH7 ((uint8_t)0x01)
|
#define TCLK0_PS_PTD5 ((uint8_t)0x02)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup FTM0CLK_PIN_SEL FTM0ÍⲿʱÖÓÒý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define FTM0CLK_PS_TCLK0 ((uint8_t)0x00)
|
#define FTM0CLK_PS_TCLK1 ((uint8_t)0x01)
|
#define FTM0CLK_PS_TCLK2 ((uint8_t)0x02)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup FTM1CLK_PIN_SEL FTM1ÍⲿʱÖÓÒý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define FTM1CLK_PS_TCLK0 ((uint8_t)0x00)
|
#define FTM1CLK_PS_TCLK1 ((uint8_t)0x01)
|
#define FTM1CLK_PS_TCLK2 ((uint8_t)0x02)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup ACMP_Hyst ACMPÄ£Äâ±È½Ï³ÙÖÍÑ¡Ôñ
|
* @{
|
*/
|
#define FTM2CLK_PS_TCLK0 ((uint8_t)0x00)
|
#define FTM2CLK_PS_TCLK1 ((uint8_t)0x01)
|
#define FTM2CLK_PS_TCLK2 ((uint8_t)0x02)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup FTM2CLK_PIN_SEL FTM2ÍⲿʱÖÓÒý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define PWTCLK_PS_TCLK0 ((uint8_t)0x00)
|
#define PWTCLK_PS_TCLK1 ((uint8_t)0x01)
|
#define PWTCLK_PS_TCLK2 ((uint8_t)0x02)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup FTM2CH0_PIN_SEL FTM2ͨµÀ0Òý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define FTM2CH0_PS_PTC0 ((uint8_t)0x00)
|
#define FTM2CH0_PS_PTH0 ((uint8_t)0x01)
|
#define FTM2CH0_PS_PTF0 ((uint8_t)0x02)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup FTM2CH1_PIN_SEL FTM2ͨµÀ1Òý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define FTM2CH1_PS_PTC1 ((uint8_t)0x00)
|
#define FTM2CH1_PS_PTH1 ((uint8_t)0x01)
|
#define FTM2CH1_PS_PTF1 ((uint8_t)0x02)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup FTM2CH2_PIN_SEL FTM2ͨµÀ2Òý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define FTM2CH2_PS_PTC2 ((uint8_t)0x00)
|
#define FTM2CH2_PS_PTD0 ((uint8_t)0x01)
|
#define FTM2CH2_PS_PTG4 ((uint8_t)0x02)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup FTM2CH3_PIN_SEL FTM2ͨµÀ3Òý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define FTM2CH3_PS_PTC3 ((uint8_t)0x00)
|
#define FTM2CH3_PS_PTD1 ((uint8_t)0x01)
|
#define FTM2CH3_PS_PTG5 ((uint8_t)0x02)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup FTM2CH4_PIN_SEL FTM2ͨµÀ4Òý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define FTM2CH4_PS_PTB4 ((uint8_t)0x00)
|
#define FTM2CH4_PS_PTG6 ((uint8_t)0x01)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup FTM2CH5_PIN_SEL FTM2ͨµÀ5Òý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define FTM2CH5_PS_PTB5 ((uint8_t)0x00)
|
#define FTM2CH5_PS_PTG7 ((uint8_t)0x01)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup I2C1_PIN_SEL I2C1Òý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define I2C1_PS_PTE1_PTE0 ((uint8_t)0x00)
|
#define I2C1_PS_PTH4_PTH3 ((uint8_t)0x01)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup SPI1_PIN_SEL SPI1Òý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define SPI1_PS_PTD0_PTD1_PTD2_PTD3 ((uint8_t)0x00)
|
#define SPI1_PS_PTG4_PTG5_PTG6_PTG7 ((uint8_t)0x01)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup UART1_PIN_SEL UART1Òý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define UART1_PS_PTC7_PTC6 ((uint8_t)0x00)
|
#define UART1_PS_PTF3_PTF2 ((uint8_t)0x01)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup UART2_PIN_SEL UART2Òý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define UART2_PS_PTD7_PTD6 ((uint8_t)0x00)
|
#define UART2_PS_PTI1_PTI0 ((uint8_t)0x01)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup PWTIN0_PIN_SEL PWTIN0Òý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define PWTIN0_PS_PTD5 ((uint8_t)0x00)
|
#define PWTIN0_PS_PTE2 ((uint8_t)0x01)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup PWTIN1_PIN_SEL PWTIN1Òý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define PWTIN1_PS_PTB0 ((uint8_t)0x00)
|
#define PWTIN1_PS_PTH7 ((uint8_t)0x01)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup ACMP_Hyst ACMPÄ£Äâ±È½Ï³ÙÖÍÑ¡Ôñ
|
* @{
|
*/
|
#define SPI0_PS_PTB2_PTB3_PTB4_PTB5 ((uint8_t)0x00)
|
#define SPI0_PS_PTE0_PTE1_PTE2_PTE3 ((uint8_t)0x01)
|
/**
|
* @}
|
*/
|
|
|
/**
|
* @defgroup EWM_PIN_SEL EWMÒý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define EWM_PS_PTA3_PTA2 ((uint8_t)0x00)
|
#define EWM_PS_PTC4_PTA4 ((uint8_t)0x01)
|
#define EWM_PS_PTE7_PTH2 ((uint8_t)0x02)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup IRQ_PIN_SEL IRQ¶Ë¿ÚÒý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define IRQ_PS_GROUP1 ((uint8_t)0x00)
|
#define IRQ_PS_GROUP2 ((uint8_t)0x01)
|
#define IRQ_PS_GROUP3 ((uint8_t)0x02)
|
#define IRQ_PS_GROUP4 ((uint8_t)0x03)
|
#define IRQ_PS_GROUP5 ((uint8_t)0x04)
|
/**
|
* @}
|
*/
|
|
|
|
/**
|
* @defgroup ACMP1_PIN_SEL ACMP1¶Ë¿ÚÒý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define ACMP1_PS_PTB5 ((uint8_t)0x00)
|
#define ACMP1_PS_PTI1 ((uint8_t)0x01)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup RTCO_PIN_SEL RTCO¶Ë¿ÚÒý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define RTCO_PS_PTC4 ((uint8_t)0x00)
|
#define RTCO_PS_PTC5 ((uint8_t)0x01)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup I2C0_PIN_SEL I2C0Òý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define I2C0_PS_PTA3_PTA2 ((uint8_t)0x00)
|
#define I2C0_PS_PTB7_PTB6 ((uint8_t)0x01)
|
/**
|
* @}
|
*/
|
|
|
/**
|
* @defgroup FTM0CH2_PIN_SEL FTM0ͨµÀ2Òý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define FTM0CH2_PS_PTH7 ((uint8_t)0x00)
|
#define FTM0CH2_PS_PTD5 ((uint8_t)0x01)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup FTM0CH3_PIN_SEL FTM0ͨµÀ3Òý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define FTM0CH3_PS_PTE4 ((uint8_t)0x00)
|
#define FTM0CH3_PS_PTD4 ((uint8_t)0x01)
|
/**
|
* @}
|
*/
|
|
|
/**
|
* @defgroup FTM1CH2_PIN_SEL FTM1ͨµÀ2Òý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define FTM1CH2_PS_PTH1 ((uint8_t)0x00)
|
#define FTM1CH2_PS_PTB4 ((uint8_t)0x01)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup FTM1CH3_PIN_SEL FTM1ͨµÀ3Òý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define FTM1CH3_PS_PTH0 ((uint8_t)0x00)
|
#define FTM1CH3_PS_PTE3 ((uint8_t)0x01)
|
/**
|
* @}
|
*/
|
|
|
/**
|
* @defgroup FTM2CH6_PIN_SEL FTM2ͨµÀ6Òý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define FTM2CH6_PS_PTF3 ((uint8_t)0x00)
|
#define FTM2CH6_PS_PTD3 ((uint8_t)0x01)
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup FTM2CH7_PIN_SEL FTM2ͨµÀ7Òý½ÅÑ¡Ôñ
|
* @{
|
*/
|
#define FTM2CH7_PS_PTF2 ((uint8_t)0x00)
|
#define FTM2CH7_PS_PTD2 ((uint8_t)0x01)
|
/**
|
* @}
|
*/
|
|
|
|
/**
|
* @defgroup SCGC_Clock_Control ÍâÉèʱÖÓ¿ª¹Ø¿ØÖÆ1
|
* @{
|
*/
|
#define SIM_SCGC_RTC 0x00000001u
|
#define SIM_SCGC_PIT 0x00000002u
|
#define SIM_SCGC_EWM 0x00000004u
|
#define SIM_SCGC_PWT 0x00000010u
|
#define SIM_SCGC_FTM0 0x00000020u
|
#define SIM_SCGC_FTM1 0x00000040u
|
#define SIM_SCGC_FTM2 0x00000080u
|
#define SIM_SCGC_CLMA 0x00000100u
|
#define SIM_SCGC_CLMB 0x00000200u
|
#define SIM_SCGC_CRC 0x00000400u
|
#define SIM_SCGC_WDG 0x00000800u
|
|
#define SIM_SCGC_MCAN 0x00004000u
|
#define SIM_SCGC_I2C0 0x00010000u
|
#define SIM_SCGC_I2C1 0x00020000u
|
#define SIM_SCGC_SPI0 0x00040000u
|
#define SIM_SCGC_SPI1 0x00080000u
|
#define SIM_SCGC_UART0 0x00100000u
|
#define SIM_SCGC_UART1 0x00200000u
|
#define SIM_SCGC_UART2 0x00400000u
|
#define SIM_SCGC_KBI0 0x01000000u
|
#define SIM_SCGC_KBI1 0x02000000u
|
#define SIM_SCGC_IRQ 0x08000000u
|
#define SIM_SCGC_DMA 0x10000000u
|
#define SIM_SCGC_ADC 0x20000000u
|
#define SIM_SCGC_ACMP0 0x40000000u
|
#define SIM_SCGC_ACMP1 0x80000000u
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup SCGC1_Clock_Control ÍâÉèʱÖÓ¿ª¹Ø¿ØÖÆ2
|
* @{
|
*/
|
#define SIM_SCGC1_FTM2F 0x00000001u
|
#define SIM_SCGC1_FTM1F 0x00000002u
|
#define SIM_SCGC1_FTM0F 0x00000004u
|
#define SIM_SCGC1_RTCEC 0x00000020u
|
#define SIM_SCGC1_ADCALTC 0x00000040u
|
#define SIM_SCGC1_FTM2T 0x01000000u
|
#define SIM_SCGC1_FTM1T 0x02000000u
|
#define SIM_SCGC1_FTM0T 0x04000000u
|
#define SIM_SCGC1_RTCLPOC 0x10000000u
|
|
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup LowerPower_FLASH_RAM_Control LPµÍ¹¦ºÄģʽFlashºÍRAMµçÔ´¿ØÖÆ
|
* @{
|
*/
|
#define SIM_LP_USER_FLASH 0x00000004u
|
#define SIM_LP_STOP_FLASH 0x00000008u
|
#define SIM_LP_USER_RAM1 0x00000020u
|
#define SIM_LP_USER_RAM2 0x00000040u
|
#define SIM_LP_USER_RAM3 0x00000080u
|
#define SIM_LP_STOP_RAM1 0x00000200u
|
#define SIM_LP_STOP_RAM2 0x00000400u
|
#define SIM_LP_STOP_RAM3 0x00000800u
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup SRAM_SIZE SRAM´óС
|
* @{
|
*/
|
#define SRAM_SIZE_24KB 0x00u
|
#define SRAM_SIZE_16KB 0x01u
|
/**
|
* @}
|
*/
|
|
/**
|
* @defgroup FLASH_SIZE FLASH´óС
|
* @{
|
*/
|
#define FLASH_SIZE_256KB 0x00u
|
#define FLASH_SIZE_128KB 0x01u
|
/**
|
* @}
|
*/
|
|
|
/**
|
* @}
|
*/
|
|
/* Exported macro ------------------------------------------------------------*/
|
/* Exported functions --------------------------------------------------------*/
|
void SIM_DeInit(void);
|
uint32_t SIM_ReadFPINID(void);
|
FlagStatus SIM_GetRstCauses(uint32_t ResetCause);
|
void SIM_ClrRstCauses(uint8_t ResetCause);
|
void SIM_SOPT0_NMIECmd(FunctionalState State);
|
void SIM_SOPT0_RSTPECmd(FunctionalState State);
|
void SIM_SOPT0_SWDECmd(FunctionalState State);
|
void SIM_SOPT0_ACMPT_FTM2Config(uint8_t TriggerType);
|
void SIM_SOPT0_UART0FilterConfig(uint32_t FilterType);
|
void SIM_SOPT0_FTM1CH1C_RTCOutputCmd(FunctionalState State);
|
void SIM_SOPT0_FTM1CH0C_ACMP0OCmd(FunctionalState State);
|
void SIM_SOPT0_FTM0CH1C_UART0ICmd(FunctionalState State);
|
void SIM_SOPT0_FTM2S_PWMCmd(FunctionalState State);
|
void SIM_SOPT0_FTM0M_UART0OutputCmd(FunctionalState State);
|
void SIM_SOPT0_BusClockDivide(uint8_t Divide);
|
void SIM_SOPT0_BusClockOutputCmd(FunctionalState State);
|
FlagStatus SIM_SOPT0_FTM2DelayTStatus(void);
|
void SIM_SOPT0_FTM2DelayTConfig(uint8_t Delay);
|
|
void SIM_SOPT1_PWTIN2InputConfig(uint8_t InputType);
|
void SIM_SOPT1_PWTIN3InputConfig(uint8_t InputType);
|
void SIM_SOPT1_ADCHardwareTConfig(uint8_t TriggerType);
|
|
|
|
void SIM_PINSEL_UART0(uint8_t PinSelect);
|
void SIM_PINSEL_FTM0CH0(uint8_t PinSelect);
|
void SIM_PINSEL_FTM0CH1(uint8_t PinSelect);
|
void SIM_PINSEL_FTM1CH0(uint8_t PinSelect);
|
void SIM_PINSEL_FTM1CH1(uint8_t PinSelect);
|
void SIM_PINSEL_FTMFLT2(uint8_t PinSelect);
|
void SIM_PINSEL_FTMFLT1(uint8_t PinSelect);
|
void SIM_PINSEL_BUSOUT(uint8_t PinSelect);
|
void SIM_PINSEL_TCLK2(uint8_t PinSelect);
|
void SIM_PINSEL_TCLK1(uint8_t PinSelect);
|
void SIM_PINSEL_TCLK0(uint8_t PinSelect);
|
void SIM_PINSEL_FTM0TCLK(uint8_t PinSelect);
|
void SIM_PINSEL_FTM1TCLK(uint8_t PinSelect);
|
void SIM_PINSEL_FTM2TCLK(uint8_t PinSelect);
|
void SIM_PINSEL_PWTTCLK(uint8_t PinSelect);
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void SIM_PINSEL_FTM2CH0(uint8_t PinSelect);
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void SIM_PINSEL_FTM2CH1(uint8_t PinSelect);
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void SIM_PINSEL_FTM2CH2(uint8_t PinSelect);
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void SIM_PINSEL_FTM2CH3(uint8_t PinSelect);
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void SIM_PINSEL_FTM2CH4(uint8_t PinSelect);
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void SIM_PINSEL_FTM2CH5(uint8_t PinSelect);
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void SIM_PINSEL_I2C1(uint8_t PinSelect);
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void SIM_PINSEL_SPI1(uint8_t PinSelect);
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void SIM_PINSEL_UART1(uint8_t PinSelect);
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void SIM_PINSEL_UART2(uint8_t PinSelect);
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void SIM_PINSEL_PWTIN0(uint8_t PinSelect);
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void SIM_PINSEL_PWTIN1(uint8_t PinSelect);
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void SIM_PINSEL_SPI0(uint8_t PinSelect);
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void SIM_PINSEL_EWM(uint8_t PinSelect);
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void SIM_PINSEL_IRQ(uint8_t PinSelect);
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void SIM_PINSEL_ACMP(uint8_t PinSelect);
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void SIM_PINSEL_RTC(uint8_t PinSelect);
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void SIM_PINSEL_I2C0(uint8_t PinSelect);
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void SIM_PINSEL_FTM0CH2(uint8_t PinSelect);
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void SIM_PINSEL_FTM0CH3(uint8_t PinSelect);
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void SIM_PINSEL_FTM1CH2(uint8_t PinSelect);
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void SIM_PINSEL_FTM1CH3(uint8_t PinSelect);
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void SIM_PINSEL_FTM2CH6(uint8_t PinSelect);
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void SIM_PINSEL_FTM2CH7(uint8_t PinSelect);
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void SIM_SCGC_Cmd(uint32_t SCGC_Type, FunctionalState State);
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uint32_t SIM_GetUUIDL(void);
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uint32_t SIM_GetUUIDML(void);
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uint32_t SIM_GetUUIDMH(void);
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uint8_t SIM_GetSRAMSize(void);
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uint8_t SIM_GetFLASHSize(void);
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uint8_t SIM_GetVer(void);
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uint8_t SIM_GetDevID(void);
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void SIM_CLKDIV_OUTDIV1(uint32_t divide);
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void SIM_CLKDIV_OUTDIV2(uint32_t divide);
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void SIM_CLKDIV_OUTDIV3(uint32_t divide);
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void SIM_CLKDIV_OUTDIV4(uint32_t divide);
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uint8_t SIM_GetOUTDIV1(void);
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uint8_t SIM_GetOUTDIV2(void);
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uint8_t SIM_GetOUTDIV3(void);
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uint8_t SIM_GetOUTDIV4(void);
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void SIM_SCGC1_Cmd(uint32_t SCGC1_Type, FunctionalState State);
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void SIM_LP_SetLowpowerCmd(uint32_t LP_Type);
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FlagStatus SIM_LP_FLASHPowerONStatus(void);
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FlagStatus SIM_LP_SRAMPowerONStatus(void);
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void SIM_WAIT_CLKWAITConfig(uint16_t Clkwait);
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void SIM_WAIT_DIV1USConfig(uint16_t Div1us);
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#ifdef __cplusplus
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}
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#endif
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#endif /*__XL_SIM_H__ */
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/**
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* @}
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*/
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/**
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* @}
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*/
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