/**
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******************************************************************************
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* @file xl_ftm.c
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* @author Kirk ,xu.wang
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* @version 4.5.2
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* @date Fri Mar 26 17:29:12 2021
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* @brief This file provide function about FTM firmware program
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******************************************************************************
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* @attention
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*
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* 2019 by Chipways Communications,Inc. All Rights Reserved.
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* This software is supplied under the terms of a license
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* agreement or non-disclosure agreement with Chipways.
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* Passing on and copying of this document,and communication
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* of its contents is not permitted without prior written
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* authorization.
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*
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* <h2><center>© COPYRIGHT 2019 Chipways</center></h2>
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******************************************************************************
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*/
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#if defined(__cplusplus)
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extern "C" {
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#endif /* __cplusplus */
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/* Includes ---------------------------------------------------------------*/
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#include "xl_ftm.h"
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/** @addtogroup XL6600_StdPeriph_Driver
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* @{
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*/
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/** @defgroup FTM FTM Module
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* @brief FTM Driver Modules Library
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* @{
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*/
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup FTM_Private_Functions
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* @brief
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* @{
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*/
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/**
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* @brief д±£»¤¹¦ÄÜʹÄÜ.
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* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
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* @arg FTM0: FTM0ÍâÉè
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* @arg FTM1: FTM1ÍâÉè
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* @arg FTM2: FTM2ÍâÉè
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* @retval None
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*/
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void FTM_WriteProtectEnable(FTM_Type* FTMx)
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{
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FTMx->FMS |= FTM_FMS_WPEN_MASK;
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}
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/**
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* @brief д±£»¤¹¦ÄܽûÓÃ.
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* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
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* @arg FTM0: FTM0ÍâÉè
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* @arg FTM1: FTM1ÍâÉè
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* @arg FTM2: FTM2ÍâÉè
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* @retval None
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*/
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void FTM_WriteProtectDisable(FTM_Type* FTMx)
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{
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FTMx->MODE |= FTM_MODE_WPDIS_MASK;
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}
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/**
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* @brief ÅäÖÃFTMxÍâÉè¼Ä´æÆ÷ΪĬÈÏÖµ
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* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
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* @arg FTM0: FTM0ÍâÉè
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* @arg FTM1: FTM1ÍâÉè
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* @arg FTM2: FTM2ÍâÉè
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* @retval None.
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*/
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void FTM_DeInit(FTM_Type* FTMx)
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{
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/* disable channel */
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FTMx->CONTROLS[0].CnSC = 0;
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FTMx->CONTROLS[0].CnV = 0;
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FTMx->CONTROLS[1].CnSC = 0;
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FTMx->CONTROLS[1].CnV = 0;
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FTMx->CONTROLS[2].CnSC = 0;
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FTMx->CONTROLS[2].CnV = 0;
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FTMx->CONTROLS[3].CnSC = 0;
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FTMx->CONTROLS[3].CnV = 0;
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if(FTMx == FTM2)
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{
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FTMx->CONTROLS[4].CnSC = 0;
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FTMx->CONTROLS[4].CnV = 0;
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FTMx->CONTROLS[5].CnSC = 0;
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FTMx->CONTROLS[5].CnV = 0;
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FTMx->CONTROLS[6].CnSC = 0;
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FTMx->CONTROLS[6].CnV = 0;
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FTMx->CONTROLS[7].CnSC = 0;
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FTMx->CONTROLS[7].CnV = 0;
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}
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/* disable the colck */
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FTMx->SC = 0;
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FTMx->CNT=0;
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FTMx->MOD = 0;
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FTMx->CNTIN=0;
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FTMx->MODE = 0x4;
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FTMx->COMBINE = 0;
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FTMx->CNTIN = 0;
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FTMx->SYNC = 0;
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FTMx->OUTINIT = 0;
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FTMx->OUTMASK = 0;
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FTMx->DEADTIME = 0;
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FTMx->EXTTRIG = 0;
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FTMx->POL = 0;
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FTMx->FMS = 0;
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FTMx->FILTER = 0;
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FTMx->FLTCTRL = 0;
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FTMx->FLTPOL = 0;
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FTMx->CONF = 0;
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FTMx->SYNCONF = 0;
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FTMx->SWOCTRL = 0;
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FTMx->PWMLOAD = 0;
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}
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/**
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* @brief FTMxÍâÉè¼Ä´æÆ÷³õʼ»¯.
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* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
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* @arg FTM0: FTM0ÍâÉè
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* @arg FTM1: FTM1ÍâÉè
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* @arg FTM2: FTM2ÍâÉè
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* @param FTM_InitStruct: Ö¸¶¨FTM_InitTypeDefÅäÖÃ.
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* @retval None.
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*/
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void FTM_Init(FTM_Type* FTMx, const FTM_InitTypeDef* FTM_InitStruct)
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{
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/*---------------------------- FTMx SC Configuration -----------------*/
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/* write SC to enable clock */
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FTMx->SC &= ~(FTM_SC_CLKS_MASK | FTM_SC_PS_MASK);
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FTMx->SC |= ((FTM_InitStruct->FTM_ClkSource << FTM_SC_CLKS_SHIFT)| (FTM_InitStruct->FTM_Prescaler));
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/* At this step, return the status of initialization */
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}
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/**
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* @brief FTMxÖ¸¶¨Í¨µÀ±ßÔµ¶ÔÆëPWMÅäÖÃ.
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* @param FTMx: Ñ¡ÔñFTMÍâÉè.
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* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
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* @arg FTM0: FTM0ÍâÉè
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* @arg FTM1: FTM1ÍâÉè
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* @arg FTM2: FTM2ÍâÉè
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* @param FTM_Channel: Ñ¡ÔñFTMͨµÀ.
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* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
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* @arg FTM_CHANNEL0: FTMxͨµÀ0
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* @arg FTM_CHANNEL1: FTMxͨµÀ1
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* @arg FTM_CHANNEL2: FTMxͨµÀ2
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* @arg FTM_CHANNEL3: FTMxͨµÀ3
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* @arg FTM_CHANNEL4: FTMxͨµÀ4
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* @arg FTM_CHANNEL5: FTMxͨµÀ5
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* @arg FTM_CHANNEL6: FTMxͨµÀ6
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* @arg FTM_CHANNEL7: FTMxͨµÀ7
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* @param PWMEdgeSelect: ±ßÑØÑ¡Ôñ
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* Õâ¸ö²ÎÊý¿ÉÒÔΪÒÔÏÂÖµ:
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* @arg FTM_PWM_HIGHTRUEPULSE: Æ¥ÅäʱÇåÁãÊä³ö
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* @arg FTM_PWM_LOWTRUEPULSE: Æ¥ÅäʱÖÃλÊä³ö
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* @retval None
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*/
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void FTM_EdgeAlignedPWMInit(FTM_Type* FTMx, uint8_t FTM_Channel, uint8_t PWMEdgeSelect)
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{
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/* disable counter */
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FTMx->SC = 0x0;
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FTMx->MOD = FTM_MOD_INIT;
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if(FTM_PWM_HIGHTRUEPULSE == PWMEdgeSelect)
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{
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/* Configure timers PWM High True Pulses */
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FTMx->CONTROLS[FTM_Channel].CnSC = FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK;
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FTMx->CONTROLS[FTM_Channel].CnV = FTM_C0V_INIT + (FTM_Channel*(uint32_t)100);
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}
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else
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{
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/* Configure timers for PWM Low True Pulses */
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FTMx->CONTROLS[FTM_Channel].CnSC = FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK;
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FTMx->CONTROLS[FTM_Channel].CnV = FTM_C0V_INIT + (FTM_Channel*(uint32_t)100) ;
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}
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}
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/**
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* @brief FTMxÖ¸¶¨Í¨µÀÖÐÐĶÔÆëPWMÅäÖÃ.
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* @param FTMx: Ñ¡ÔñFTMÍâÉè.
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* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
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* @arg FTM0: FTM0ÍâÉè
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* @arg FTM1: FTM1ÍâÉè
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* @arg FTM2: FTM2ÍâÉè
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* @param FTM_Channel: Ñ¡ÔñFTMͨµÀ.
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* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
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* @arg FTM_CHANNEL0: FTMxͨµÀ0
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* @arg FTM_CHANNEL1: FTMxͨµÀ1
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* @arg FTM_CHANNEL2: FTMxͨµÀ2
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* @arg FTM_CHANNEL3: FTMxͨµÀ3
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* @arg FTM_CHANNEL4: FTMxͨµÀ4
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* @arg FTM_CHANNEL5: FTMxͨµÀ5
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* @arg FTM_CHANNEL6: FTMxͨµÀ6
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* @arg FTM_CHANNEL7: FTMxͨµÀ7
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* @param PWMEdgeSelect: ±ßÑØÑ¡Ôñ
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* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
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* @arg FTM_PWM_HIGHTRUEPULSE: Æ¥ÅäʱÇåÁãÊä³ö
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* @arg FTM_PWM_LOWTRUEPULSE: Æ¥ÅäʱÖÃλÊä³ö
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* @retval None
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*/
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void FTM_CenterAlignedPWMInit(FTM_Type* FTMx, uint8_t FTM_Channel, uint8_t PWMEdgeSelect)
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{
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/* disable counter */
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FTMx->SC = 0x0;
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FTMx->MOD = FTM_MOD_INIT;
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FTMx->SC |= FTM_SC_CPWMS_MASK;
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if(FTM_PWM_HIGHTRUEPULSE == PWMEdgeSelect)
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{
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/* Configure timers PWM High True Pulses */
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FTMx->CONTROLS[FTM_Channel].CnSC = FTM_CnSC_ELSB_MASK;
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FTMx->CONTROLS[FTM_Channel].CnV = FTM_C0V_INIT + (FTM_Channel * (uint32_t)100);
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}
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else
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{
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/* Configure timers for PWM Low True Pulses */
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FTMx->CONTROLS[FTM_Channel].CnSC = FTM_CnSC_ELSA_MASK;
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FTMx->CONTROLS[FTM_Channel].CnV = FTM_C0V_INIT + (FTM_Channel * (uint32_t)100);
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}
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}
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/**
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* @brief FTMx×éºÏģʽPWMÅäÖÃ.
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* @param FTMx: Ñ¡ÔñFTMÍâÉè.
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* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
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* @arg FTM0: FTM0ÍâÉè
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* @arg FTM1: FTM1ÍâÉè
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* @arg FTM2: FTM2ÍâÉè
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* @param FTM_CombinePWMStruct: Ö¸ÏòFTM_CombinePWMTypeDefÅäÖÃ.
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* @retval None
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*/
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void FTM_CombinePWMPWMInit(FTM_Type* FTMx, const FTM_CombinePWMTypeDef *FTM_CombinePWMStruct)
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{
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/* disable counter */
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FTMx->SC = 0x0;
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FTMx->MOD = FTM_MOD_INIT;
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FTMx->SC &= ~FTM_SC_CPWMS_MASK;
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if(FTM_CombinePWMStruct->FTM_ChannelPair == FTM_CHANNELPAIR0)
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{
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FTMx->COMBINE &= ~(FTM_COMBINE_COMBINE0_MASK | FTM_COMBINE_COMP0_MASK | FTM_COMBINE_DTEN0_MASK | \
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FTM_COMBINE_SYNCEN0_MASK | FTM_COMBINE_FAULTEN0_MASK);
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FTMx->COMBINE |= ((FTM_CombinePWMStruct->FTM_CombineEn) | \
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(FTM_CombinePWMStruct->FTM_CompEn << FTM_COMBINE_COMP0_SHIFT)| \
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(FTM_CombinePWMStruct->FTM_DeadtimeEn << FTM_COMBINE_DTEN0_SHIFT) |
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(FTM_CombinePWMStruct->FTM_SynchronizationEn << FTM_COMBINE_SYNCEN0_SHIFT)| \
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(FTM_CombinePWMStruct->FTM_FaultControlEn << FTM_COMBINE_FAULTEN0_SHIFT));
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}
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else if(FTM_CombinePWMStruct->FTM_ChannelPair==FTM_CHANNELPAIR1)
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{
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FTMx->COMBINE &= ~(FTM_COMBINE_COMBINE1_MASK | FTM_COMBINE_COMP1_MASK | FTM_COMBINE_DTEN1_MASK | \
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FTM_COMBINE_SYNCEN1_MASK | FTM_COMBINE_FAULTEN1_MASK);
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FTMx->COMBINE |= ((FTM_CombinePWMStruct->FTM_CombineEn << FTM_COMBINE_COMBINE1_SHIFT) | \
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(FTM_CombinePWMStruct->FTM_CompEn << FTM_COMBINE_COMP1_SHIFT)| \
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(FTM_CombinePWMStruct->FTM_DeadtimeEn << FTM_COMBINE_DTEN1_SHIFT) |
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(FTM_CombinePWMStruct->FTM_SynchronizationEn << FTM_COMBINE_SYNCEN1_SHIFT)| \
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(FTM_CombinePWMStruct->FTM_FaultControlEn << FTM_COMBINE_FAULTEN1_SHIFT));
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}
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else if(FTM_CombinePWMStruct->FTM_ChannelPair==FTM_CHANNELPAIR2)
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{
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FTMx->COMBINE &= ~(FTM_COMBINE_COMBINE2_MASK | FTM_COMBINE_COMP2_MASK | FTM_COMBINE_DTEN2_MASK | \
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FTM_COMBINE_SYNCEN2_MASK | FTM_COMBINE_FAULTEN2_MASK);
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FTMx->COMBINE |= ((FTM_CombinePWMStruct->FTM_CombineEn << FTM_COMBINE_COMBINE2_SHIFT) | \
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(FTM_CombinePWMStruct->FTM_CompEn << FTM_COMBINE_COMP2_SHIFT)| \
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(FTM_CombinePWMStruct->FTM_DeadtimeEn << FTM_COMBINE_DTEN2_SHIFT) |
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(FTM_CombinePWMStruct->FTM_SynchronizationEn << FTM_COMBINE_SYNCEN2_SHIFT)| \
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(FTM_CombinePWMStruct->FTM_FaultControlEn << FTM_COMBINE_FAULTEN2_SHIFT));
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}
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else
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{
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FTMx->COMBINE &= ~(FTM_COMBINE_COMBINE3_MASK | FTM_COMBINE_COMP3_MASK | FTM_COMBINE_DTEN3_MASK | \
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FTM_COMBINE_SYNCEN3_MASK | FTM_COMBINE_FAULTEN3_MASK);
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FTMx->COMBINE |= ((FTM_CombinePWMStruct->FTM_CombineEn << FTM_COMBINE_COMBINE3_SHIFT) | \
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(FTM_CombinePWMStruct->FTM_CompEn << FTM_COMBINE_COMP3_SHIFT)| \
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(FTM_CombinePWMStruct->FTM_DeadtimeEn << FTM_COMBINE_DTEN3_SHIFT) |
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(FTM_CombinePWMStruct->FTM_SynchronizationEn << FTM_COMBINE_SYNCEN3_SHIFT)| \
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(FTM_CombinePWMStruct->FTM_FaultControlEn << FTM_COMBINE_FAULTEN3_SHIFT));
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}
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if(FTM_PWM_HIGHTRUEPULSE == FTM_CombinePWMStruct->PWMEdgeSelect)
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{
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/* Configure timers PWM High True Pulses */
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FTMx->CONTROLS[FTM_CombinePWMStruct->FTM_ChannelPair].CnSC = FTM_CnSC_ELSB_MASK;
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FTMx->CONTROLS[FTM_CombinePWMStruct->FTM_ChannelPair].CnV = FTM_C0V_INIT + (FTM_CombinePWMStruct->FTM_ChannelPair*(uint32_t)100);
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FTMx->CONTROLS[FTM_CombinePWMStruct->FTM_ChannelPair + (uint32_t)1].CnSC = FTM_CnSC_ELSB_MASK;
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FTMx->CONTROLS[FTM_CombinePWMStruct->FTM_ChannelPair + (uint32_t)1].CnV = FTM_C0V_INIT + ((FTM_CombinePWMStruct->FTM_ChannelPair+(uint32_t)1)*(uint32_t)100);
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}
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else
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{
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/* Configure timers for PWM Low True Pulses */
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FTMx->CONTROLS[FTM_CombinePWMStruct->FTM_ChannelPair].CnSC = FTM_CnSC_ELSA_MASK;
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FTMx->CONTROLS[FTM_CombinePWMStruct->FTM_ChannelPair].CnV = FTM_C0V_INIT + (FTM_CombinePWMStruct->FTM_ChannelPair* (uint32_t)100);
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FTMx->CONTROLS[FTM_CombinePWMStruct->FTM_ChannelPair + (uint32_t)1].CnSC = FTM_CnSC_ELSA_MASK;
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FTMx->CONTROLS[FTM_CombinePWMStruct->FTM_ChannelPair + (uint32_t)1].CnV = FTM_C0V_INIT + ((FTM_CombinePWMStruct->FTM_ChannelPair+ (uint32_t)1)* (uint32_t)100) ;
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}
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}
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/**
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* @brief FTMxPWM³õʼ»¯
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* @param FTMx: Ñ¡ÔñFTMÍâÉè.
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* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
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* @arg FTM0: FTM0ÍâÉè
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* @arg FTM1: FTM1ÍâÉè
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* @arg FTM2: FTM2ÍâÉè
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* @param PWMModeSelect: Ñ¡Ôñpwmģʽ.
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* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
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* @arg FTM_PWMMODE_EDGEALLIGNED: ±ßÑضÔÆëģʽ
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* @arg FTM_PWMMODE_CENTERALLIGNED: ÖÐÐÄģʽ¶ÔÆë
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* @arg FTM_PWMMODE_COMBINE: ×éºÏģʽ
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* @param PWMEdgeSelect: ±ßÑØÑ¡Ôñ
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* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
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* @arg FTM_PWM_HIGHTRUEPULSE: Æ¥ÅäʱÇåÁãÊä³ö
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* @arg FTM_PWM_LOWTRUEPULSE: Æ¥ÅäʱÖÃλÊä³ö
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* @retval None
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*/
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void FTM_PWMInit(FTM_Type* FTMx, uint8_t PWMModeSelect, uint8_t PWMEdgeSelect)
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{
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uint8_t channels, i;
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/* channels num */
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if (FTM0 == FTMx)
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{
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channels = 2;
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}
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else if(FTM1 == FTMx)
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{
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channels = 2;
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}
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else
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{
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channels = 6;
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}
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/* disable counter */
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FTMx->SC = 0x0;
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FTMx->MOD = FTM_MOD_INIT;
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/* enable CPWM */
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if(FTM_PWMMODE_CENTERALLIGNED == PWMModeSelect)
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{
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FTMx->SC |= FTM_SC_CPWMS_MASK;
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}
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/* enable combine pwm mode */
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else if(FTM_PWMMODE_COMBINE == PWMModeSelect)
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{
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FTMx->MODE |= FTM_MODE_WPDIS_MASK | FTM_MODE_SYNCLOADEN_MASK;
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FTMx->COMBINE = FTM_COMBINE_COMBINE0_MASK | FTM_COMBINE_COMP0_MASK | FTM_COMBINE_SYNCEN0_MASK | FTM_COMBINE_DTEN0_MASK |
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FTM_COMBINE_COMBINE1_MASK | FTM_COMBINE_COMP1_MASK | FTM_COMBINE_SYNCEN1_MASK | FTM_COMBINE_DTEN1_MASK |
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FTM_COMBINE_COMBINE2_MASK | FTM_COMBINE_COMP2_MASK | FTM_COMBINE_SYNCEN2_MASK | FTM_COMBINE_DTEN2_MASK ;
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FTMx->SC &= ~FTM_SC_CPWMS_MASK;
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}
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else
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{
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FTMx->SC &= ~FTM_SC_CPWMS_MASK;
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}
|
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if(FTM_PWM_HIGHTRUEPULSE == PWMEdgeSelect)
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{
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/* Configure timers PWM High True Pulses */
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for(i=0; i<channels; i++)
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{
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FTMx->CONTROLS[i].CnSC = FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK;
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FTMx->CONTROLS[i].CnV = FTM_C0V_INIT + (i*(uint32_t)100);
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}
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}
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else
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{
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/* Configure timers for PWM Low True Pulses */
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for(i=0; i<channels; i++)
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{
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FTMx->CONTROLS[i].CnSC = FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK;
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FTMx->CONTROLS[i].CnV = FTM_C0V_INIT + (i*(uint32_t)100);
|
}
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}
|
}
|
|
/**
|
* @brief FTMxÊäÈ벶»ñ³õʼ»¯
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FTM_Channel: Ñ¡ÔñFTMͨµÀ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_CHANNEL0: FTMxͨµÀ0
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* @arg FTM_CHANNEL1: FTMxͨµÀ1
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* @arg FTM_CHANNEL2: FTMxͨµÀ2
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* @arg FTM_CHANNEL3: FTMxͨµÀ3
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* @arg FTM_CHANNEL4: FTMxͨµÀ4
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* @arg FTM_CHANNEL5: FTMxͨµÀ5
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* @arg FTM_CHANNEL6: FTMxͨµÀ6
|
* @arg FTM_CHANNEL7: FTMxͨµÀ7
|
* @param CaptureMode: Ñ¡Ôñ²¶»ñ±ßÑØ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_INPUTCAPTURE_RISINGEDGE: ÉÏÉýÑز¶»ñ
|
* @arg FTM_INPUTCAPTURE_FALLINGEDGE: ϽµÑز¶»ñ
|
* @arg FTM_INPUTCAPTURE_BOTHEDGE: Ë«±ßÑز¶»ñ
|
* @retval None
|
*/
|
void FTM_InputCaptureInit(FTM_Type* FTMx, uint8_t FTM_Channel, uint8_t CaptureMode)
|
{
|
FTMx->SC = 0x0; /* disable counter */
|
FTMx->MOD = 0xFFFF; /* free running */
|
|
/* enable interrupt, Capture on rising edge */
|
if(FTM_INPUTCAPTURE_RISINGEDGE == CaptureMode)
|
{
|
FTMx->CONTROLS[FTM_Channel].CnSC = FTM_CnSC_CHIE_MASK | FTM_CnSC_ELSA_MASK;
|
}
|
|
/* Capture on falling edge */
|
else if(FTM_INPUTCAPTURE_FALLINGEDGE == CaptureMode)
|
{
|
FTMx->CONTROLS[FTM_Channel].CnSC = FTM_CnSC_CHIE_MASK | FTM_CnSC_ELSB_MASK;
|
}
|
|
/* Capture on rising or falling edge */
|
else
|
{
|
FTMx->CONTROLS[FTM_Channel].CnSC = FTM_CnSC_CHIE_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK;
|
}
|
}
|
|
|
/**
|
* @brief FTMxË«Ñز¶»ñ³õʼ»¯
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FTM_DualEdgeStruct: Ö¸ÏòFTM_DualEdgeCaptureTypeDefÅäÖÃ.
|
* @retval None
|
*/
|
void FTM_DualEdgeCaptureInit(FTM_Type* FTMx, const FTM_DualEdgeCaptureTypeDef* FTM_DualEdgeStruct)
|
{
|
/* diable counter */
|
FTMx->SC = 0x0;
|
FTMx->MOD = 0xFFFF;
|
|
/* DECAPEN = 1, ChannelPair/2 * 8 */
|
FTMx->COMBINE |= ((uint32_t)(FTM_COMBINE_DECAPEN0_MASK) << (FTM_DualEdgeStruct->FTM_ChannelPair * 4u));
|
|
/* CH(n)F and CH(n+1)F bits must be cleared first */
|
FTMx->CONTROLS[FTM_DualEdgeStruct->FTM_ChannelPair].CnSC &= ~FTM_CnSC_CHF_MASK;
|
FTMx->CONTROLS[FTM_DualEdgeStruct->FTM_ChannelPair + (uint8_t)1].CnSC &= ~FTM_CnSC_CHF_MASK;
|
|
/* oneshot mode */
|
if(FTM_INPUTCAPTURE_DUALEDGE_ONESHOT == FTM_DualEdgeStruct->FTM_CaptureMode)
|
{
|
FTMx->CONTROLS[FTM_DualEdgeStruct->FTM_ChannelPair].CnSC &= ~FTM_CnSC_MSA_MASK;
|
FTMx->CONTROLS[FTM_DualEdgeStruct->FTM_ChannelPair + (uint8_t)1].CnSC &= ~FTM_CnSC_MSA_MASK;
|
}
|
/* continuouse mode */
|
else
|
{
|
FTMx->CONTROLS[FTM_DualEdgeStruct->FTM_ChannelPair].CnSC |= FTM_CnSC_MSA_MASK;
|
FTMx->CONTROLS[FTM_DualEdgeStruct->FTM_ChannelPair + (uint8_t)1u].CnSC |= FTM_CnSC_MSA_MASK;
|
}
|
|
/* select detec edge */
|
FTMx->CONTROLS[FTM_DualEdgeStruct->FTM_ChannelPair].CnSC |= (FTM_DualEdgeStruct->FTM_Channel_N_Edge << (uint8_t)2);
|
FTMx->CONTROLS[FTM_DualEdgeStruct->FTM_ChannelPair + (uint8_t)1].CnSC |= (FTM_DualEdgeStruct->FTM_Channel_Np1_Edge << (uint8_t)2);
|
|
FTMx->COMBINE |= ((uint32_t)FTM_COMBINE_DECAP0_MASK << (FTM_DualEdgeStruct->FTM_ChannelPair * 4u));
|
}
|
|
/**
|
* @brief FTMxÊä³ö±È½Ï³õʼ»¯
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FTM_Channel: Ñ¡ÔñFTMͨµÀ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_CHANNEL0: FTMxͨµÀ0
|
* @arg FTM_CHANNEL1: FTMxͨµÀ1
|
* @arg FTM_CHANNEL2: FTMxͨµÀ2
|
* @arg FTM_CHANNEL3: FTMxͨµÀ3
|
* @arg FTM_CHANNEL4: FTMxͨµÀ4
|
* @arg FTM_CHANNEL5: FTMxͨµÀ5
|
* @arg FTM_CHANNEL6: FTMxͨµÀ6
|
* @arg FTM_CHANNEL7: FTMxͨµÀ7
|
* @param CompareMode: Ñ¡Ôñ±È½Ï±ßÑØ
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_OUTPUT_TOGGLE: Æ¥ÅäʱÇл»Êä³ö
|
* @arg FTM_OUTPUT_CLEAR: Æ¥ÅäʱÇåÁãÊä³ö
|
* @arg FTM_OUTPUT_SET: Æ¥ÅäʱÖÃλÊä³ö
|
* @retval None
|
*/
|
void FTM_OutputCompareInit(FTM_Type* FTMx, uint8_t FTM_Channel, uint32_t CompareMode)
|
{
|
FTM_WriteProtectDisable(FTMx );
|
|
/* diable counter */
|
FTMx->SC = 0x0;
|
FTMx->MOD = FTM_MOD_INIT;
|
|
/* select detec edge */
|
FTMx->CONTROLS[FTM_Channel].CnSC = (FTM_CnSC_MSA_MASK | (CompareMode << (uint8_t)2u));
|
FTMx->CONTROLS[FTM_Channel].CnV = FTM_C0V_INIT;
|
}
|
|
/**
|
* @brief ʹÄÜFTMÒç³öÖжÏ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param NewState:FTMxÒç³öÖжÏÊÇ·ñʹÄÜ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg ENABLE: ʹÄÜFTMxÒç³öÖжÏ
|
* @arg DISABLE: ʧÄÜFTMxÒç³öÖжÏ
|
* @retval None
|
*/
|
void FTM_OverflowITCmd(FTM_Type* FTMx, FunctionalState NewState)
|
{
|
if (NewState != DISABLE)
|
{
|
/* first clear the Timer Overflow flag */
|
if((FTMx->SC & FTM_SC_TOF_MASK) == FTM_SC_TOF_MASK)
|
{
|
FTMx->SC &= ~FTM_SC_TOF_MASK;
|
}
|
/* Enable the Timer Overflow interrupt function */
|
FTMx->SC |= FTM_SC_TOIE_MASK;
|
}
|
else
|
{
|
/* Disable the Timer Overflow interrupt function */
|
FTMx->SC &= ~FTM_SC_TOIE_MASK;
|
}
|
}
|
|
/**
|
* @brief »ñÈ¡Òç³ö±ê־״̬.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @retval µ±Ç°×´Ì¬(TRUE or FALSE)
|
*/
|
FlagStatus FTM_GetOverFlowFlag(const FTM_Type* FTMx)
|
{
|
return ((FTMx->SC & FTM_SC_TOF_MASK) == FTM_SC_TOF_MASK);
|
}
|
|
|
/**
|
* @brief ʹÄÜFTMͨµÀ¶ÔÖÐCV ¼Ä´æÆ÷ͬ²½.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FTM_ ChannelPair: Ñ¡ÔñFTMͨµÀ¶Ô.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_CHANNELPAIR0: FTMxͨµÀ¶Ô0
|
* @arg FTM_CHANNELPAIR1: FTMxͨµÀ¶Ô1
|
* @arg FTM_CHANNELPAIR2: FTMxͨµÀ¶Ô2
|
* @arg FTM_CHANNELPAIR3: FTMxͨµÀ¶Ô3
|
* @param NewState:ÊÇ·ñʹÄÜͨµÀ¶ÔÖÐCV¼Ä´æÆ÷ͬ²½.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg ENABLE: ʹÄÜCV¼Ä´æÆ÷ͬ²½
|
* @arg DISABLE: ʧÄÜCV¼Ä´æÆ÷ͬ²½
|
|
* @retval None
|
*/
|
void FTM_CVSyncEnable(FTM_Type* FTMx,uint8_t FTM_ChannelPair,FunctionalState State)
|
{
|
if(State == ENABLE)
|
{
|
if(FTM_ChannelPair == FTM_CHANNELPAIR0)
|
{
|
FTMx->COMBINE |= FTM_COMBINE_SYNCEN0_MASK;
|
}
|
else if(FTM_ChannelPair == FTM_CHANNELPAIR1)
|
{
|
FTMx->COMBINE |= FTM_COMBINE_SYNCEN1_MASK;
|
}
|
else if(FTM_ChannelPair == FTM_CHANNELPAIR2)
|
{
|
FTMx->COMBINE |= FTM_COMBINE_SYNCEN2_MASK;
|
}
|
else
|
{
|
FTMx->COMBINE |= FTM_COMBINE_SYNCEN3_MASK;
|
}
|
}
|
else
|
{
|
if(FTM_ChannelPair == FTM_CHANNELPAIR0)
|
{
|
FTMx->COMBINE &= ~FTM_COMBINE_SYNCEN0_MASK;
|
}
|
else if(FTM_ChannelPair == FTM_CHANNELPAIR1)
|
{
|
FTMx->COMBINE &= ~FTM_COMBINE_SYNCEN1_MASK;
|
}
|
else if(FTM_ChannelPair == FTM_CHANNELPAIR2)
|
{
|
FTMx->COMBINE &= ~FTM_COMBINE_SYNCEN2_MASK;
|
}
|
else
|
{
|
FTMx->COMBINE &= ~FTM_COMBINE_SYNCEN3_MASK;
|
}
|
}
|
}
|
|
/**
|
* @brief Çå³ýFTMxÒç³ö±êÖ¾.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @retval None
|
*/
|
void FTM_ClrOverFlowFlag(FTM_Type* FTMx)
|
{
|
if((FTMx->SC & FTM_SC_TOF_MASK) == FTM_SC_TOF_MASK)
|
{
|
FTMx->SC &= ~FTM_SC_TOF_MASK;
|
}
|
}
|
|
/**
|
* @brief »ñÈ¡CNTÖµ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @retval ·µ»ØCNTµÄÖµ.
|
*/
|
uint16_t FTM_GetCountValue(const FTM_Type* FTMx)
|
{
|
return (uint16_t)FTMx->CNT;
|
}
|
|
/**
|
* @brief ÉèÖÃMODÖµ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param ModValue: É趨MODÖµ.
|
* @retval None
|
*/
|
void FTM_SetModValue(FTM_Type* FTMx, uint16_t ModValue)
|
{
|
FTMx->CNT = 0;
|
FTMx->MOD = ModValue;
|
}
|
|
/**
|
* @brief ÉèÖÃCNTINÖµ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @retval None
|
*/
|
void FTM_SetCountInitValue(FTM_Type* FTMx, uint16_t InitialValue)
|
{
|
FTMx->CNTIN = InitialValue;
|
}
|
|
/**
|
* @brief FTMxͨµÀÖжÏʹÄÜ
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FTM_Channel: Ñ¡ÔñFTMͨµÀ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_CHANNEL0: FTMxͨµÀ0
|
* @arg FTM_CHANNEL1: FTMxͨµÀ1
|
* @arg FTM_CHANNEL2: FTMxͨµÀ2
|
* @arg FTM_CHANNEL3: FTMxͨµÀ3
|
* @arg FTM_CHANNEL4: FTMxͨµÀ4
|
* @arg FTM_CHANNEL5: FTMxͨµÀ5
|
* @arg FTM_CHANNEL6: FTMxͨµÀ6
|
* @arg FTM_CHANNEL7: FTMxͨµÀ7
|
* @param NewState: FTMxÏàӦͨµÀÖжÏÊÇ·ñʹÄÜ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg ENABLE: ʹÄÜFTMxͨµÀÖжÏ
|
* @arg DISABLE: ʧÄÜFTMxͨµÀÖжÏ
|
* @retval None
|
*/
|
void FTM_ChannelIntCmd(FTM_Type* FTMx, uint8_t FTM_Channel, FunctionalState NewState)
|
{
|
if (NewState != DISABLE)
|
{
|
/* Enable the channel interrupt function */
|
FTMx->CONTROLS[FTM_Channel].CnSC |= FTM_CnSC_CHIE_MASK;
|
}
|
else
|
{
|
/* Disable the channel interrupt function */
|
FTMx->CONTROLS[FTM_Channel].CnSC &= ~FTM_CnSC_CHIE_MASK;
|
}
|
|
}
|
|
/**
|
* @brief FTM»ñȡͨµÀ±êÖ¾
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FTM_Channel: Ñ¡ÔñFTMͨµÀ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_CHANNEL0: FTMxͨµÀ0
|
* @arg FTM_CHANNEL1: FTMxͨµÀ1
|
* @arg FTM_CHANNEL2: FTMxͨµÀ2
|
* @arg FTM_CHANNEL3: FTMxͨµÀ3
|
* @arg FTM_CHANNEL4: FTMxͨµÀ4
|
* @arg FTM_CHANNEL5: FTMxͨµÀ5
|
* @arg FTM_CHANNEL6: FTMxͨµÀ6
|
* @arg FTM_CHANNEL7: FTMxͨµÀ7
|
* @retval ·µ»ØͨµÀ±êÖ¾.
|
*/
|
FlagStatus FTM_GetChannelFlag(const FTM_Type* FTMx, uint8_t FTM_Channel)
|
{
|
return ((FTMx->CONTROLS[FTM_Channel].CnSC & FTM_CnSC_CHF_MASK) == FTM_CnSC_CHF_MASK);
|
}
|
|
/**
|
* @brief FTMÇå³ýͨµÀ±êÖ¾
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FTM_Channel: Ñ¡ÔñFTMͨµÀ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_CHANNEL0: FTMxͨµÀ0
|
* @arg FTM_CHANNEL1: FTMxͨµÀ1
|
* @arg FTM_CHANNEL2: FTMxͨµÀ2
|
* @arg FTM_CHANNEL3: FTMxͨµÀ3
|
* @arg FTM_CHANNEL4: FTMxͨµÀ4
|
* @arg FTM_CHANNEL5: FTMxͨµÀ5
|
* @arg FTM_CHANNEL6: FTMxͨµÀ6
|
* @arg FTM_CHANNEL7: FTMxͨµÀ7
|
* @retval None
|
*/
|
void FTM_ClrChannelFlag(FTM_Type* FTMx, uint8_t FTM_Channel)
|
{
|
//Dummy read while CHF is set
|
(void) FTMx->CONTROLS[FTM_Channel].CnSC;
|
FTMx->CONTROLS[FTM_Channel].CnSC &= ~FTM_CnSC_CHF_MASK;
|
}
|
|
/**
|
* @brief FTMÉèÖÃͨµÀÖµ
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FTM_Channel: Ñ¡ÔñFTMͨµÀ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_CHANNEL0: FTMxͨµÀ0
|
* @arg FTM_CHANNEL1: FTMxͨµÀ1
|
* @arg FTM_CHANNEL2: FTMxͨµÀ2
|
* @arg FTM_CHANNEL3: FTMxͨµÀ3
|
* @arg FTM_CHANNEL4: FTMxͨµÀ4
|
* @arg FTM_CHANNEL5: FTMxͨµÀ5
|
* @arg FTM_CHANNEL6: FTMxͨµÀ6
|
* @arg FTM_CHANNEL7: FTMxͨµÀ7
|
* @param ChannelValue: É趨ͨµÀÖµ.
|
* @retval None
|
*/
|
void FTM_SetChannelValue(FTM_Type* FTMx, uint8_t FTM_Channel, uint16_t ChannelValue)
|
{
|
FTMx->CONTROLS[FTM_Channel].CnV = ChannelValue;
|
}
|
/**
|
* @brief FTM»ñȡͨµÀÖµ
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FTM_Channel: Ñ¡ÔñFTMͨµÀ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_CHANNEL0: FTMxͨµÀ0
|
* @arg FTM_CHANNEL1: FTMxͨµÀ1
|
* @arg FTM_CHANNEL2: FTMxͨµÀ2
|
* @arg FTM_CHANNEL3: FTMxͨµÀ3
|
* @arg FTM_CHANNEL4: FTMxͨµÀ4
|
* @arg FTM_CHANNEL5: FTMxͨµÀ5
|
* @arg FTM_CHANNEL6: FTMxͨµÀ6
|
* @arg FTM_CHANNEL7: FTMxͨµÀ7
|
* @retval ͨµÀÖµ
|
*/
|
uint16_t FTM_GetChannelValue(const FTM_Type* FTMx, uint8_t FTM_Channel )
|
{
|
return (uint16_t)FTMx->CONTROLS[FTM_Channel].CnV;
|
}
|
/**
|
* @brief »ñÈ¡ËùÓÐͨµÀÒç³ö±êÖ¾.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @retval ·µ»ØËùÓÐͨµÀ±êÖ¾.
|
*/
|
uint32_t FTM_GetStatusRegFlag(const FTM_Type* FTMx)
|
{
|
return (FTMx->STATUS & 0xFFu);
|
}
|
|
/**
|
* @brief Çå³ýËùÓÐͨµÀÒç³ö±êÖ¾.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @retval None
|
*/
|
void FTM_ClrStatusRegFlag(FTM_Type* FTMx)
|
{
|
if((FTMx->STATUS & 0xFFu) != 0u)
|
{
|
FTMx->STATUS = 0x00;
|
}
|
}
|
|
/**
|
* @brief µÃµ½Ö¸¶¨Í¨µÀÒç³ö±êÖ¾.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FTM_Channel: Ñ¡ÔñFTMͨµÀ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_CHANNEL0: FTMxͨµÀ0
|
* @arg FTM_CHANNEL1: FTMxͨµÀ1
|
* @arg FTM_CHANNEL2: FTMxͨµÀ2
|
* @arg FTM_CHANNEL3: FTMxͨµÀ3
|
* @arg FTM_CHANNEL4: FTMxͨµÀ4
|
* @arg FTM_CHANNEL5: FTMxͨµÀ5
|
* @arg FTM_CHANNEL6: FTMxͨµÀ6
|
* @arg FTM_CHANNEL7: FTMxͨµÀ7
|
* @retval ·µ»ØËùÓÐͨµÀ±êÖ¾.
|
*/
|
FlagStatus FTM_GetStatusChannelFlag(const FTM_Type* FTMx, uint8_t ChannelFlag)
|
{
|
uint32_t flag;
|
|
/* Get all the channel flags */
|
flag = FTMx->STATUS ;
|
|
/* get the selected channel flag */
|
return ((flag &((uint32_t)1<<ChannelFlag)) == ((uint32_t)1<<ChannelFlag));
|
}
|
|
/**
|
* @brief Çå³ýÖ¸¶¨Í¨µÀÒç³ö±êÖ¾.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FTM_Channel: Ñ¡ÔñFTMͨµÀ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_CHANNEL0: FTMxͨµÀ0
|
* @arg FTM_CHANNEL1: FTMxͨµÀ1
|
* @arg FTM_CHANNEL2: FTMxͨµÀ2
|
* @arg FTM_CHANNEL3: FTMxͨµÀ3
|
* @arg FTM_CHANNEL4: FTMxͨµÀ4
|
* @arg FTM_CHANNEL5: FTMxͨµÀ5
|
* @arg FTM_CHANNEL6: FTMxͨµÀ6
|
* @arg FTM_CHANNEL7: FTMxͨµÀ7
|
* @retval None
|
*/
|
void FTM_ClrStatusChannelFlag(FTM_Type* FTMx, uint8_t ChannelFlag)
|
{
|
if((FTMx->STATUS & ((uint32_t)1<<ChannelFlag)) != 0u)
|
{
|
FTMx->STATUS &= ~((uint32_t)1<<ChannelFlag);
|
}
|
}
|
|
/**
|
* @brief ʹÄÜ´íÎóÖжÏ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param NewState: ´íÎóÖжÏÊÇ·ñʹÄÜ
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg ENABLE: ʹÄÜFTMx´íÎóÖжÏ
|
* @arg DISABLE: ʧÄÜFTMx´íÎóÖжÏ
|
* @retval None
|
*/
|
void FTM_FaultITCmd(FTM_Type* FTMx, FunctionalState NewState)
|
{
|
if (NewState != DISABLE)
|
{
|
/* Enable the fault interrupt */
|
FTMx->MODE |= FTM_MODE_FAULTIE_MASK;
|
}
|
else
|
{
|
/* Disable the fault interrupt */
|
FTMx->MODE &= ~FTM_MODE_FAULTIE_MASK;
|
}
|
}
|
|
/**
|
* @brief ¶¨ÒåFTM´íÎó¿ØÖÆģʽ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FTM_FaultControlModeDef: Ñ¡Ôñ´íÎó¿ØÖÆģʽ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_ALLDISABLE: ËùÓÐͨµÀ½ûÓùÊÕÏ
|
* @arg FTM_EVENENABLE_MANUALCLEAR: żÊýͨµÀʹÄܹÊÕÏ¿ØÖÆ£¬ÊÖ¶¯¹ÊÕÏÇåÁã.
|
* @arg FTM_ALLENABLE_MANUALCLEAR: ËùÓÐͨµÀʹÄܹÊÕÏ¿ØÖÆ£¬ÊÖ¶¯¹ÊÕÏÇåÁã.
|
* @arg FTM_ALLENABLE_AUTOCLEAR: ËùÓÐͨµÀʹÄܹÊÕÏ¿ØÖÆ£¬×Ô¶¯¹ÊÕÏÇåÁã.
|
* @retval None
|
*/
|
void FTM_SetFaultControlMode(FTM_Type* FTMx, FTM_FaultControlModeDef FTM_FaultControlMode)
|
{
|
FTMx->MODE &= ~FTM_MODE_FAULTM_MASK;
|
|
FTMx->MODE |= ((uint32_t)FTM_FaultControlMode << FTM_MODE_FAULTM_SHIFT);
|
}
|
|
/**
|
* @brief ʹÄܲ¶»ñ²âÊÔģʽ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param NewState: ²¶»ñ²âÊÔÊÇ·ñʹÄÜ
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg ENABLE: ʹÄÜFTMx²¶»ñ²âÊÔ
|
* @arg DISABLE: ʧÄÜFTMx²¶»ñ²âÊÔ
|
* @retval None
|
*/
|
void FTM_CaptureTestCmd(FTM_Type* FTMx, FunctionalState NewState)
|
{
|
if (NewState != DISABLE)
|
{
|
/* Enable the CAPTEST function */
|
FTMx->MODE |= FTM_MODE_CAPTEST_MASK;
|
}
|
else
|
{
|
/* Disable the CAPTEST function */
|
FTMx->MODE &= ~FTM_MODE_CAPTEST_MASK;
|
}
|
}
|
|
/**
|
* @brief Ñ¡ÔñPWMͬ²½Èí¼þ´¥·¢.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param NewState: PWMͬ²½Èí¼þ´¥·¢ÊÇ·ñʹÄÜ
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg ENABLE: ʹÄÜFTMxµÄPWMͬ²½Èí¼þ´¥·¢
|
* @arg DISABLE: ʧÄÜFTMxµÄPWMͬ²½Èí¼þ´¥·¢
|
* @retval None
|
*/
|
void FTM_SoftwareSync(FTM_Type* FTMx, FunctionalState NewState)
|
{
|
if (NewState != DISABLE)
|
{
|
/* Enable the SWSYNC function */
|
FTMx->SYNC |= FTM_SYNC_SWSYNC_MASK;
|
}
|
else
|
{
|
/* Disable the SWSYNC function */
|
FTMx->SYNC &= ~FTM_SYNC_SWSYNC_MASK;
|
}
|
}
|
|
/**
|
* @brief Ñ¡ÔñPWMͬ²½Ó²¼þ´¥·¢.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param TriggerN: ͬ²½´¥·¢ÐźÅÑ¡Ôñ
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_SYNC_TRIGGER_TRIGGER0: Tigger0 synchronization
|
* @arg FTM_SYNC_TRIGGER_TRIGGER1: Tigger1 synchronization
|
* @arg FTM_SYNC_TRIGGER_TRIGGER2: Tigger2 synchronization
|
* @param NewState: PWMͬ²½Ó²¼þ´¥·¢ÊÇ·ñʹÄÜ
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg ENABLE: ʹÄÜFTMxµÄPWMͬ²½Ó²¼þ´¥·¢
|
* @arg DISABLE: ʧÄÜFTMxµÄPWMͬ²½Ó²¼þ´¥·¢
|
* @retval None
|
*/
|
void FTM_HardwareSync(FTM_Type* FTMx, uint8_t TriggerN, FunctionalState NewState)
|
{
|
if (NewState != DISABLE)
|
{
|
/* Enable the selected Trigger */
|
FTMx->SYNC |= ((uint32_t)TriggerN);
|
}
|
else
|
{
|
/* Disable the selected Trigger */
|
FTMx->SYNC &= ~((uint32_t)TriggerN);
|
}
|
}
|
|
/**
|
* @brief Ñ¡ÔñSWOCTRL/INVCTRL/OUTMASK/MOD, CNTINºÍCV/CNTͬ²½.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param TriggerType: ´¥·¢Ä£Ê½Ñ¡Ôñ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_SYNCONF_SWTRIGGER: Èí¼þ´¥·¢Ä£Ê½
|
* @arg FTM_SYNCONF_HWTRIGGER: Ó²¼þ´¥·¢Ä£Ê½
|
* @param RegType: ¼Ä´æÆ÷ͬ²½¿ØÖÆ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_SYNCONF_CNTREG: CNT¼Ä´æÆ÷ͬ²½
|
* @arg FTM_SYNCONF_MODCNTINCVREG: MOD¡¢CNTINºÍCV¼Ä´æÆ÷ͬ²½
|
* @arg FTM_SYNCONF_OUTMASKREG: OUTMASK ¼Ä´æÆ÷ͬ²½
|
* @arg FTM_SYNCONF_INVCTRLREG: INVCTRL¼Ä´æÆ÷ͬ²½
|
* @arg FTM_SYNCONF_SWOCTRLREG: SWOCTRL¼Ä´æÆ÷ͬ²½
|
* @param NewState: ͬ²½ÊÇ·ñʹÄÜ.
|
* @arg ENABLE: ʹÄÜFTMxµÄPWMͬ²½Ó²¼þ´¥·¢
|
* @arg DISABLE: ʧÄÜFTMxµÄPWMͬ²½Ó²¼þ´¥·¢
|
* @retval None
|
*/
|
void FTM_RegSyncCmd(FTM_Type* FTMx, uint8_t TriggerType, uint8_t RegType, FunctionalState NewState)
|
{
|
uint32_t tempvalue;
|
|
if(TriggerType == FTM_SYNCONF_SWTRIGGER)
|
{
|
tempvalue= ((uint32_t)0x100 << RegType);
|
|
if (NewState != DISABLE)
|
{
|
/* Enable the software trigger activate synchronization. */
|
FTMx->SYNCONF |= tempvalue;
|
}
|
else
|
{
|
/* Disable the software trigger activate synchronization. */
|
FTMx->SYNCONF &= ~tempvalue;
|
}
|
}
|
else
|
{
|
tempvalue= ((uint32_t)0x10000 << RegType);
|
|
if (NewState != DISABLE)
|
{
|
/* Enable the hardware trigger activate synchronization. */
|
FTMx->SYNCONF |= tempvalue;
|
}
|
else
|
{
|
/* Disable the hardware trigger activate synchronization. */
|
FTMx->SYNCONF &= ~tempvalue;
|
}
|
}
|
}
|
|
/**
|
* @brief OUTMASK¼Ä´æÆ÷ͬ²½
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param update:ͬ²½Ä£Ê½Ñ¡Ôñ
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_UPDATE_RISINGCLK: ¼Ä´æÆ÷ÔÚËùÓÐϵͳµÄÉÏÉýÑؽøÐÐͬ²½¸üÐÂ
|
* @arg FTM_UPDATE_PWMSYNC: ¼Ä´æÆ÷½öͨ¹ýPWMͬ²½¸üÐÂ
|
* @retval None
|
*/
|
void FTM_OutMaskSync(FTM_Type* FTMx, uint8_t update)
|
{
|
if(FTM_UPDATE_PWMSYNC==update)
|
{
|
/* updated with the value of its buffer only by the PWM synchronization. */
|
FTMx->SYNC |= FTM_SYNC_SYNCHOM_MASK;
|
}
|
else
|
{
|
/* updated with the value of its buffer in all rising edges of the system clock. */
|
FTMx->SYNC &= ~FTM_SYNC_SYNCHOM_MASK;
|
}
|
}
|
|
/**
|
* @brief CNTIN¼Ä´æÆ÷ͬ²½
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param update:ͬ²½¸üÐÂģʽѡÔñ
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_UPDATE_RISINGCLK: ¼Ä´æÆ÷ÔÚËùÓÐϵͳµÄÉÏÉýÑؽøÐÐͬ²½¸üÐÂ
|
* @arg FTM_UPDATE_PWMSYNC: ¼Ä´æÆ÷½öͨ¹ýPWMͬ²½¸üÐÂ
|
* @retval None
|
*/
|
void FTM_CNTINCSync(FTM_Type* FTMx, uint8_t update)
|
{
|
if(FTM_UPDATE_PWMSYNC==update)
|
{
|
/* updated with the value of its buffer only by the PWM synchronization. */
|
FTMx->SYNCONF |= FTM_SYNCONF_CNTINC_MASK;
|
}
|
else
|
{
|
/* updated with the value of its buffer in all rising edges of the system clock. */
|
FTMx->SYNCONF &= ~FTM_SYNCONF_CNTINC_MASK;
|
}
|
}
|
|
/**
|
* @brief INVCTRL¼Ä´æÆ÷ͬ²½.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param update:ͬ²½¸üÐÂģʽѡÔñ
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_UPDATE_RISINGCLK: ¼Ä´æÆ÷ÔÚËùÓÐϵͳµÄÉÏÉýÑؽøÐÐͬ²½¸üÐÂ
|
* @arg FTM_UPDATE_PWMSYNC: ¼Ä´æÆ÷½öͨ¹ýPWMͬ²½¸üÐÂ
|
* @retval None
|
*/
|
void FTM_INVCSync(FTM_Type* FTMx, uint8_t update)
|
{
|
if(FTM_UPDATE_PWMSYNC==update)
|
{
|
/* updated with the value of its buffer only by the PWM synchronization. */
|
FTMx->SYNCONF |= FTM_SYNCONF_INVC_MASK;
|
}
|
else
|
{
|
/* updated with the value of its buffer in all rising edges of the system clock. */
|
FTMx->SYNCONF &= ~FTM_SYNCONF_INVC_MASK;
|
}
|
}
|
|
/**
|
* @brief SWOCTRL¼Ä´æÆ÷ͬ²½.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param update:ͬ²½¸üÐÂģʽѡÔñ
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_UPDATE_RISINGCLK: ¼Ä´æÆ÷ÔÚËùÓÐϵͳµÄÉÏÉýÑؽøÐÐͬ²½¸üÐÂ
|
* @arg FTM_UPDATE_PWMSYNC: ¼Ä´æÆ÷½öͨ¹ýPWMͬ²½¸üÐÂ
|
* @retval None
|
*/
|
void FTM_SWOCSync(FTM_Type* FTMx, uint8_t update)
|
{
|
if(FTM_UPDATE_PWMSYNC==update)
|
{
|
/* updated with the value of its buffer only by the PWM synchronization. */
|
FTMx->SYNCONF |= FTM_SYNCONF_SWOC_MASK;
|
}
|
else
|
{
|
/* updated with the value of its buffer in all rising edges of the system clock. */
|
FTMx->SYNCONF &= ~FTM_SYNCONF_SWOC_MASK;
|
}
|
}
|
|
/**
|
* @brief Ñ¡ÔñPWMͬ²½Ä£Ê½.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param mode:ģʽѡÔñ
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_SYNCMODE_LEGACY: Ñ¡Ôñ´«Í³PWMͬ²½
|
* @arg FTM_SYNCMODE_ENHANCED: Ñ¡ÔñÔöÇ¿PWMͬ²½
|
* @retval None
|
*/
|
void FTM_SetSyncMode(FTM_Type* FTMx, uint8_t mode)
|
{
|
if(FTM_SYNCMODE_ENHANCED == mode)
|
{
|
/* selecte Enhanced PWM synchronization */
|
FTMx->SYNCONF |= FTM_SYNCONF_SYNCMODE_MASK;
|
}
|
else
|
{
|
/* selecte Legacy PWM synchronization . */
|
FTMx->SYNCONF &= ~FTM_SYNCONF_SYNCMODE_MASK;
|
}
|
}
|
|
/**
|
* @brief FTMÈí¼þͬ²½´¥·¢ÀàÐÍ
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param type:ģʽѡÔñ
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_SOFTWARE_SYN_CNT: Èí¼þ´¥·¢¼¤»îFTM¼ÆÊýÆ÷ͬ²½
|
* @arg FTM_SOFTWARE_SYN_MOD_CNTIN_CV: Èí¼þ´¥·¢¼¤»îMOD¡¢CNTIN¡¢CV¼Ä´æÆ÷ͬ²½
|
* @arg FTM_SOFTWARE_SYN_OUTMASK: Èí¼þ´¥·¢¼¤»îÊä³öÆÁ±Îͬ²½
|
* @arg FTM_SOFTWARE_SYN_INVCTRL: Èí¼þ´¥·¢¼¤»î·´Ïà¿ØÖÆͬ²½
|
* @arg FTM_SOFTWARE_SYN_OUTCTRL: Èí¼þ´¥·¢¼¤»îÊä³ö¿ØÖÆͬ²½
|
* @param NewState: Èí¼þͬ²½¼¤»îģʽÊÇ·ñʹÄÜ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg ENABLE: ʹÄÜ
|
* @arg DISABLE: ʧÄÜ
|
* @retval None
|
*/
|
void FTM_SoftSyncActivateTypeEnable(FTM_Type* FTMx, uint32_t type, FunctionalState NewState)
|
{
|
if(NewState != DISABLE)
|
{
|
FTMx->SYNCONF |= type;
|
}
|
else
|
{
|
FTMx->SYNCONF &= ~type;
|
}
|
}
|
|
/**
|
* @brief FTMÓ²¼þͬ²½´¥·¢ÀàÐÍ
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param type:ģʽѡÔñ
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_HARDWARE_SYN_CNT: Ó²¼þ´¥·¢¼¤»îFTM¼ÆÊýÆ÷ͬ²½
|
* @arg FTM_HARDWARE_SYN_MOD_CNTIN_CV: Ó²¼þ´¥·¢¼¤»îMOD¡¢CNTIN¡¢CV¼Ä´æÆ÷ͬ²½
|
* @arg FTM_HARDWARE_SYN_OUTMASK: Ó²¼þ´¥·¢¼¤»îÊä³öÆÁ±Îͬ²½
|
* @arg FTM_HARDWARE_SYN_INVCTRL: Ó²¼þ´¥·¢¼¤»î·´Ïà¿ØÖÆͬ²½
|
* @arg FTM_HARDWARE_SYN_OUTCTRL: Ó²¼þ´¥·¢¼¤»îÊä³ö¿ØÖÆͬ²½
|
* @param NewState: Ó²¼þͬ²½¼¤»îģʽÊÇ·ñʹÄÜ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg ENABLE: ×î´ó¼ÓÔصãʹÄÜ
|
* @arg DISABLE: ×î´ó¼ÓÔصãʧÄÜ
|
* @retval None
|
*/
|
void FTM_HardSyncActivateTypeEnable(FTM_Type* FTMx, uint32_t type, FunctionalState NewState)
|
{
|
if(NewState != DISABLE)
|
{
|
FTMx->SYNCONF |= type;
|
}
|
else
|
{
|
FTMx->SYNCONF &= ~type;
|
}
|
}
|
|
|
|
/**
|
* @brief Ñ¡ÔñPWMͬ²½Ä£Ê½.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param mode:ģʽѡÔñ
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_PWMSYNC_NORESTRICT: ¿ÉÓÃÓÚMOD,CnV,OUTMASKºÍFTM¼ÆÊýÆ÷ͬ²½µÄÈí¼þºÍÓ²¼þ´¥·¢
|
* @arg FTM_PWMSYNC_SWANDHW: Èí¼þ´¥·¢Ö»ÄÜÓÃÓÚMODºÍCnVͬ²½£¬Ó²¼þ´¥·¢Ö»ÄÜÓÃÓÚOUTMASKºÍFTM¼ÆÊýÆ÷ͬ²½
|
* @retval None
|
*/
|
void FTM_SetPWMSyncMode(FTM_Type* FTMx, uint8_t mode)
|
{
|
if(FTM_PWMSYNC_SWANDHW == mode)
|
{
|
/* Software trigger can only be used by MOD and CnV synchronization, and hardware
|
triggers can only be used by OUTMASK and FTM counter synchronization */
|
FTMx->MODE |= FTM_MODE_PWMSYNC_MASK;
|
}
|
else
|
{
|
/* Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM
|
counter synchronization. */
|
FTMx->MODE &= ~FTM_MODE_PWMSYNC_MASK;
|
}
|
}
|
|
/**
|
* @brief Ñ¡ÔñÓ²¼þ´¥·¢Ä£Ê½.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param mode:ģʽѡÔñ
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_HWTRIGMODE_CLEAR: ¼ì²éµ½Ó²¼þ´¥·¢Ê±£¬FTMÇåÁãTRIGλ
|
* @arg FTM_HWTRIGMODE_UNCLEAR: ¼ì²éµ½Ó²¼þ´¥·¢Ê±£¬FTM²»ÇåÁãTRIGλ
|
* @retval None
|
*/
|
void FTM_SetHardwareTriggerMode(FTM_Type* FTMx, uint8_t mode)
|
{
|
if(FTM_HWTRIGMODE_UNCLEAR == mode)
|
{
|
/* FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. */
|
FTMx->SYNCONF |= FTM_SYNCONF_HWTRIGMODE_MASK;
|
}
|
else
|
{
|
/* FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. */
|
FTMx->SYNCONF &= ~FTM_SYNCONF_HWTRIGMODE_MASK;
|
}
|
}
|
|
/**
|
* @brief Ñ¡ÔñPWMͬ²½×î´óÔØÈë.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param NewState: ×î´ó¼ÓÔصãÊÇ·ñʹÄÜ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg ENABLE: ×î´ó¼ÓÔصãʹÄÜ
|
* @arg DISABLE: ×î´ó¼ÓÔصãʧÄÜ
|
* @retval None
|
*/
|
void FTM_CNTMAXCmd(FTM_Type* FTMx, FunctionalState NewState)
|
{
|
if (NewState != DISABLE)
|
{
|
/* Enable the CNTMAX function */
|
FTMx->SYNC |= FTM_SYNC_CNTMAX_MASK;
|
}
|
else
|
{
|
/* Disable the CNTMAX function */
|
FTMx->SYNC &= ~FTM_SYNC_CNTMAX_MASK;
|
}
|
}
|
|
|
/**
|
* @brief Ñ¡ÔñPWMͬ²½×îСÔØÈë.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param NewState: ×îС¼ÓÔصãÊÇ·ñʹÄÜ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg ENABLE: ×îС¼ÓÔصãʹÄÜ
|
* @arg DISABLE: ×îС¼ÓÔصãʧÄÜ
|
* @retval None
|
*/
|
void FTM_CNTMINCmd(FTM_Type* FTMx, FunctionalState NewState)
|
{
|
if (NewState != DISABLE)
|
{
|
/* Enable the CNTMIN function */
|
FTMx->SYNC |= FTM_SYNC_CNTMIN_MASK;
|
}
|
else
|
{
|
/* Disable the CNTMIN function */
|
FTMx->SYNC &= ~FTM_SYNC_CNTMIN_MASK;
|
}
|
}
|
|
/**
|
* @brief FTM¼ÆÊýÆ÷ͬ²½ÖØÐÂÔ¤ÖÃ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param mode: ÖØгõʼ»¯ÅäÖÃ
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_REINIT_NORMALLY: Õý³£¼ÆÊý
|
* @arg FTM_REINIT_UPDATED: µ±¼ì²âµ½Ìض¨µÄ´¥·¢Ê±£¬FTM¼ÆÊýÆ÷ÒÔÆä³õʼֵ¸üÐÂ
|
* @retval None
|
*/
|
void FTM_Reinitialization(FTM_Type* FTMx, uint8_t mode)
|
{
|
if(FTM_REINIT_UPDATED == mode)
|
{
|
/* FTM counter is updated with its initial value when the selected trigger is detected. */
|
FTMx->SYNC |= FTM_SYNC_REINIT_MASK;
|
}
|
else
|
{
|
/* FTM counter continues to count normally. */
|
FTMx->SYNC &= ~FTM_SYNC_REINIT_MASK;
|
}
|
}
|
|
/**
|
* @brief Ñ¡Ôñ³õʼ»¯·¢ÉúʱͨµÀÊä³öÖµ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param initialvalue:³õʼ»¯Í¨µÀÊä³ö
|
* @retval None
|
*/
|
void FTM_SetInitOut(FTM_Type* FTMx, uint8_t initialvalue)
|
{
|
FTMx->OUTINIT = initialvalue;
|
|
/* When a 1 is written to INIT bit the channels output is initialized according to
|
the state of their corresponding bit in the OUTINIT register.*/
|
FTMx->MODE |= FTM_MODE_INIT_MASK;
|
}
|
|
/**
|
* @brief Ö¸¶¨Í¨µÀÑ¡Ôñ³õʼ»¯·¢ÉúʱͨµÀÊä³öÖµ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FTM_Channel: Ñ¡ÔñFTMͨµÀ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_CHANNEL0: FTMxͨµÀ0
|
* @arg FTM_CHANNEL1: FTMxͨµÀ1
|
* @arg FTM_CHANNEL2: FTMxͨµÀ2
|
* @arg FTM_CHANNEL3: FTMxͨµÀ3
|
* @arg FTM_CHANNEL4: FTMxͨµÀ4
|
* @arg FTM_CHANNEL5: FTMxͨµÀ5
|
* @arg FTM_CHANNEL6: FTMxͨµÀ6
|
* @arg FTM_CHANNEL7: FTMxͨµÀ7
|
* @param initialvalue:Ö¸¶¨Í¨µÀ³õʼ»¯Êä³ö
|
* @retval None
|
*/
|
void FTM_SetChannelOutInitValue(FTM_Type* FTMx,uint8_t FTM_Channel, uint8_t initialvalue)
|
{
|
uint32_t tempvalue;
|
|
tempvalue = ((uint32_t)1<<FTM_Channel);
|
|
if(initialvalue != (uint32_t)0)
|
{
|
/* The initialization value is 1. */
|
FTMx->OUTINIT |= tempvalue;
|
}
|
else
|
{
|
/* The initialization value is 0. */
|
FTMx->OUTINIT &= ~tempvalue;
|
}
|
|
/* When a 1 is written to INIT bit the channels output is initialized according to
|
the state of their corresponding bit in the OUTINIT register.*/
|
FTMx->MODE |= FTM_MODE_INIT_MASK;
|
}
|
|
/**
|
* @brief ¶¨ÒåͨµÀÊä³öÊÇ·ñ¿É¼ûµÄ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param outmask: ÉèÖÃoutmask¼Ä´æÆ÷µÄÖµ.
|
* @retval None
|
*/
|
void FTM_SetOutMask(FTM_Type* FTMx, uint8_t outmask)
|
{
|
/* Enable the Output Mask function */
|
FTMx->OUTMASK = outmask;
|
}
|
|
/**
|
* @brief ¶¨ÒåÖ¸¶¨Í¨µÀÊä³öÊÇ·ñ¿É¼ûµÄ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FTM_Channel: Ñ¡ÔñFTMͨµÀ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_CHANNEL0: FTMxͨµÀ0
|
* @arg FTM_CHANNEL1: FTMxͨµÀ1
|
* @arg FTM_CHANNEL2: FTMxͨµÀ2
|
* @arg FTM_CHANNEL3: FTMxͨµÀ3
|
* @arg FTM_CHANNEL4: FTMxͨµÀ4
|
* @arg FTM_CHANNEL5: FTMxͨµÀ5
|
* @arg FTM_CHANNEL6: FTMxͨµÀ6
|
* @arg FTM_CHANNEL7: FTMxͨµÀ7
|
* @param NewState: ͨµÀÊä³öÆÁ±ÎÊÇ·ñʹÄÜ
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg ENABLE: ͨµÀÊä³öÆÁ±Î
|
* @arg DISABLE: ͨµÀÊä³öδÆÁ±Î
|
* @retval None
|
*/
|
void FTM_SetChannelOutMaskCmd(FTM_Type* FTMx, uint8_t FTM_Channel, FunctionalState NewState)
|
{
|
uint32_t maskvalue;
|
|
maskvalue = ((uint32_t)1<<FTM_Channel);
|
|
if (NewState != DISABLE)
|
{
|
/* Enable Output Mask */
|
FTMx->OUTMASK |= maskvalue;
|
}
|
else
|
{
|
/* Disable Output Mask */
|
FTMx->OUTMASK &= ~maskvalue;
|
}
|
}
|
|
/**
|
* @brief Ñ¡ÔñËÀÇøÔ¤¶¨ÇøÓòºÍËÀÇøÖµ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param PrescalerValue: ËÀÇøʱ¼äÔ¤·ÖƵֵ
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_DEADTIME_DTPS_DIV1: FTMxʱÖÓ1·ÖƵ
|
* @arg FTM_DEADTIME_DTPS_DIV4: FTMxʱÖÓ4·ÖƵ
|
* @arg FTM_DEADTIME_DTPS_DIV16: FTMxʱÖÓ16·ÖƵ
|
* @param DeadtimeValue: ËÀÇøʱ¼ä(0x00~0x3F)
|
* @retval None
|
*/
|
void FTM_PWMDeadtimeSet(FTM_Type* FTMx, uint32_t PrescalerValue, uint32_t DeadtimeValue)
|
{
|
FTM0->DEADTIME = 0;
|
/* set the deadtime */
|
FTMx->DEADTIME = ((DeadtimeValue & (uint32_t)0x3F) | ((PrescalerValue & (uint32_t)0x3) << FTM_DEADTIME_DTPS_SHIFT));
|
}
|
|
/**
|
* @brief »ñȡͨµÀ´¥·¢±êÖ¾.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @return ·µ»ØͨµÀ´¥·¢±êÖ¾.
|
*/
|
FlagStatus FTM_GetExternalTriggerFlag(const FTM_Type* FTMx)
|
{
|
return ((FTMx->EXTTRIG & FTM_EXTTRIG_TRIGF_MASK) == FTM_EXTTRIG_TRIGF_MASK);
|
}
|
|
/**
|
* @brief Çå³ýͨµÀ´¥·¢±êÖ¾.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @retval None
|
*/
|
void FTM_ClrExternalTriggerFlag(FTM_Type* FTMx)
|
{
|
/* first read the reg, then write 0 to clear */
|
if((FTMx->EXTTRIG & FTM_EXTTRIG_TRIGF_MASK) == FTM_EXTTRIG_TRIGF_MASK)
|
{
|
FTMx->EXTTRIG &= ~FTM_EXTTRIG_TRIGF_MASK;
|
}
|
}
|
|
/**
|
* @brief ÊÇ·ñʹÄÜͨµÀN´¥·¢.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FTM_Channel: Ñ¡ÔñFTMͨµÀ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_CHANNEL0: FTMxͨµÀ0
|
* @arg FTM_CHANNEL1: FTMxͨµÀ1
|
* @arg FTM_CHANNEL2: FTMxͨµÀ2
|
* @arg FTM_CHANNEL3: FTMxͨµÀ3
|
* @arg FTM_CHANNEL4: FTMxͨµÀ4
|
* @arg FTM_CHANNEL5: FTMxͨµÀ5
|
* @param NewState: ͨµÀN´¥·¢ÊÇ·ñʹÄÜ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg ENABLE: ʹÄÜͨµÀN´¥·¢
|
* @arg DISABLE: ʹÄÜͨµÀN´¥·¢
|
* @retval None
|
*/
|
void FTM_SetChnTriggerCmd(FTM_Type* FTMx, uint8_t FTM_Channel, FunctionalState NewState)
|
{
|
uint32_t value;
|
|
/* Enable the hardware trigger mask function */
|
value = (FTM_Channel > 1U) ? ((uint32_t)1 << (FTM_Channel - 2U)) : ((uint32_t)1 << (FTM_Channel + 4U));
|
|
if (NewState != DISABLE)
|
{
|
/* Enable The generation of the channel trigger */
|
FTMx->EXTTRIG |= value;
|
}
|
else
|
{
|
/* Disable The generation of the channel trigger */
|
FTMx->EXTTRIG &= ~value;
|
}
|
}
|
|
/**
|
* @brief µ±FTM¼ÆÊýÓëCNTIN¼Ä´æÆ÷ÖµÏàͬʱ´¥·¢Ê¹ÄÜ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param NewState: ³õʼ»¯´¥·¢ÊÇ·ñʹÄÜ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg ENABLE: ʹÄܳõʼ»¯´¥·¢Éú³É
|
* @arg DISABLE: ʧÄܳõʼ»¯´¥·¢Éú³É
|
* @retval None
|
*/
|
void FTM_SetInitTriggerCmd(FTM_Type* FTMx, FunctionalState NewState)
|
{
|
if (NewState != DISABLE)
|
{
|
/* Enable the generation of the channel trigger */
|
FTMx->EXTTRIG |= FTM_EXTTRIG_INITTRIGEN_MASK;
|
}
|
else
|
{
|
/* Disable the generation of the channel trigger */
|
FTMx->EXTTRIG &= ~FTM_EXTTRIG_INITTRIGEN_MASK;
|
}
|
}
|
|
/**
|
* @brief ¶¨ÒåͨµÀÊä³ö¼«ÐÔ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param PolarityValue: ÉèÖÃPOL¼Ä´æÆ÷µÄÖµ.
|
* @retval None
|
*/
|
void FTM_SetChannelsPolarity(FTM_Type* FTMx, uint8_t PolarityValue)
|
{
|
/* Enable the channels polarity */
|
FTMx->POL = PolarityValue;
|
}
|
|
/**
|
* @brief ¶¨Ò嵥ͨµÀÊä³ö¼«ÐÔ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FTM_Channel: Ñ¡ÔñFTMͨµÀ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_CHANNEL0: FTMxͨµÀ0
|
* @arg FTM_CHANNEL1: FTMxͨµÀ1
|
* @arg FTM_CHANNEL2: FTMxͨµÀ2
|
* @arg FTM_CHANNEL3: FTMxͨµÀ3
|
* @arg FTM_CHANNEL4: FTMxͨµÀ4
|
* @arg FTM_CHANNEL5: FTMxͨµÀ5
|
* @arg FTM_CHANNEL6: FTMxͨµÀ6
|
* @arg FTM_CHANNEL7: FTMxͨµÀ7
|
* @param FTM_Polarity: Êä³ö¼«ÐÔ
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_CHANNELPOLARITY_HIGH: ͨµÀ¼«ÐÔΪ¸ßµçƽÓÐЧ
|
* @arg FTM_CHANNELPOLARITY_LOW: ͨµÀ¼«ÐÔΪµÍµçƽÓÐЧ
|
* @retval None
|
*/
|
void FTM_SetSingleChannelPolarity(FTM_Type* FTMx, uint8_t FTM_Channel, uint8_t FTM_Polarity)
|
{
|
uint32_t polvalue;
|
|
polvalue = ((uint32_t)1<<FTM_Channel);
|
|
if (FTM_Polarity != FTM_CHANNELPOLARITY_HIGH)
|
{
|
/* The channel polarity is active low */
|
FTMx->POL |= polvalue;
|
}
|
else
|
{
|
/* The channel polarity is active high */
|
FTMx->POL &= ~polvalue;
|
}
|
}
|
|
/**
|
* @brief ±íÕ÷FAULTFÖе±j = 3, 2, 1, 0ʱµÄÂß¼OR,µ±Ð´0ʱÇå³ý,µ±Ð´1ʱûÓÐ×÷ÓÃ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @retval ·µ»ØFAULTFÖе±j = 3, 2, 1, 0ʱµÄÂß¼OR.
|
*/
|
FlagStatus FTM_GetFaultDetectLogicORFlag(const FTM_Type* FTMx)
|
{
|
return ((FTMx->FMS & FTM_FMS_FAULTF_MASK) == FTM_FMS_FAULTF_MASK);
|
}
|
|
/**
|
* @brief ͨ¹ýÓ²¼þÉèÖôíÎóÐźÅʹÄÜ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FaultDetectFlag: ¹ÊÕϼì²â±êÖ¾.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_FAULTDETECTION_FLAG0: ¹ÊÕϼì²â±êÖ¾0
|
* @arg FTM_FAULTDETECTION_FLAG1: ¹ÊÕϼì²â±êÖ¾1
|
* @arg FTM_FAULTDETECTION_FLAG2: ¹ÊÕϼì²â±êÖ¾2
|
* @arg FTM_FAULTDETECTION_FLAG3: ¹ÊÕϼì²â±êÖ¾3
|
* @retval None
|
*/
|
FlagStatus FTM_GetFaultDetectFlag(const FTM_Type* FTMx, uint8_t FaultDetectFlag)
|
{
|
return ((FTMx->FMS & ((uint32_t)1 << FaultDetectFlag)) == ((uint32_t)1 << FaultDetectFlag));
|
}
|
|
/**
|
* @brief µ±´íÎó¿ØÖÆʹÄÜÖØÖôíÎóÊäÈëʹÄÜORÂß¼.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @retval None
|
*/
|
uint32_t FTM_GetFaultInLogicORValue(const FTM_Type* FTMx)
|
{
|
return (FTMx->FMS & FTM_FMS_FAULTIN_MASK);
|
}
|
|
/**
|
* @brief Çå³ýFaultDetectLogicOR±êÖ¾.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @retval None
|
*/
|
void FTM_ClrFaultDetectLogicORFlag(FTM_Type* FTMx)
|
{
|
/* first read the reg, then write 0 to clear */
|
if((FTMx->FMS & FTM_FMS_FAULTF_MASK) == FTM_FMS_FAULTF_MASK)
|
{
|
FTMx->FMS &= ~FTM_FMS_FAULTF_MASK;
|
}
|
}
|
|
/**
|
* @brief Çå³ý´íÎó¼ì²â±êÖ¾.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FaultDetectFlag: ¹ÊÕϼì²â±êÖ¾.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_FAULTDETECTION_FLAG0: ¹ÊÕϼì²â±êÖ¾0
|
* @arg FTM_FAULTDETECTION_FLAG1: ¹ÊÕϼì²â±êÖ¾1
|
* @arg FTM_FAULTDETECTION_FLAG2: ¹ÊÕϼì²â±êÖ¾2
|
* @arg FTM_FAULTDETECTION_FLAG3: ¹ÊÕϼì²â±êÖ¾3
|
* @retval None
|
*/
|
void FTM_ClrFaultDetectFlag(FTM_Type* FTMx, uint8_t FaultDetectFlag)
|
{
|
/* first read the reg, then write 0 to clear */
|
if((FTMx->FMS & ((uint32_t)1<<FaultDetectFlag)) != (uint32_t)0)
|
{
|
FTMx->FMS &= ~(((uint32_t)1 << FaultDetectFlag));
|
}
|
}
|
|
|
/**
|
* @brief Ñ¡Ôñµ¥Í¨µÀÊäÈëÂËÖµ,µ±ÖµÎª0ʱÂËÖµÎÞЧ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FTM_FilterChannel: FTMÊäÈëÂ˲¨Í¨µÀ
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_INPUTFILTER_CHANNEL0: ͨµÀ0ÊäÈëÂ˲¨Æ÷
|
* @arg FTM_INPUTFILTER_CHANNEL1: ͨµÀ1ÊäÈëÂ˲¨Æ÷
|
* @arg FTM_INPUTFILTER_CHANNEL2: ͨµÀ2ÊäÈëÂ˲¨Æ÷
|
* @arg FTM_INPUTFILTER_CHANNEL3: ͨµÀ3ÊäÈëÂ˲¨Æ÷
|
* @param FilterValue: ÉèÖÃÂËÖµ0x0~0xF.
|
* @retval None
|
*/
|
void FTM_SetChannelInFilter(FTM_Type* FTMx, uint8_t FTM_FilterChannel, uint32_t FilterValue)
|
{
|
FTMx->FILTER &= ~((uint32_t)0xF << (FTM_FilterChannel << 2));
|
/* Selects the filter value for the channel input. */
|
FTMx->FILTER |= (FilterValue << (FTM_FilterChannel << 2));
|
}
|
|
|
/**
|
* @brief Ñ¡ÔñͨµÀÊäÈëÂËÖµ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param filter: ÉèÖÃFILTER¼Ä´æÆ÷µÄÖµ.
|
* @retval None
|
*/
|
void FTM_SetInCapFilter(FTM_Type* FTMx, uint16_t filter)
|
{
|
/* set the filter value */
|
FTMx->FILTER = filter;
|
}
|
|
/**
|
* @brief ÊÇ·ñʹÄܹÊÕÏÊäÈë.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FaultInput: Ö¸ÏòFTM_fault_input_listÊý¾Ý.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_FAULT_INPUT0: ¹ÊÕÏÊäÈë0
|
* @arg FTM_FAULT_INPUT1: ¹ÊÕÏÊäÈë1
|
* @arg FTM_FAULT_INPUT2: ¹ÊÕÏÊäÈë2
|
* @arg FTM_FAULT_INPUT3: ¹ÊÕÏÊäÈë3
|
* @param NewState: ¹ÊÕÏÊäÈëÊÇ·ñʹÄÜ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg ENABLE: ʹÄܹÊÕÏÊäÈë
|
* @arg DISABLE: ʧÄܹÊÕÏÊäÈë
|
* @retval None
|
*/
|
void FTM_FaultPinCmd(FTM_Type* FTMx, uint8_t FaultInput, FunctionalState NewState)
|
{
|
uint32_t tempvalue;
|
|
tempvalue= ((uint32_t)1 << FaultInput);
|
|
if (NewState != DISABLE)
|
{
|
/* Enable Fault input */
|
FTMx->FLTCTRL |= tempvalue;
|
}
|
else
|
{
|
/* Disable Fault input */
|
FTMx->FLTCTRL &= ~tempvalue;
|
}
|
}
|
|
|
/**
|
* @brief ÊÇ·ñʹÄÜÂËÖµ¹ÊÕÏÊäÈë.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FaultFilter: Ö¸ÏòFTM_fault_input_filter_listÊý¾Ý.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_FAULTINPUT_FILTER0: ¹ÊÕÏÊäÈë0Â˲¨Æ÷
|
* @arg FTM_FAULTINPUT_FILTER1: ¹ÊÕÏÊäÈë1Â˲¨Æ÷
|
* @arg FTM_FAULTINPUT_FILTER2: ¹ÊÕÏÊäÈë2Â˲¨Æ÷
|
* @arg FTM_FAULTINPUT_FILTER3: ¹ÊÕÏÊäÈë3Â˲¨Æ÷
|
* @param NewState: ¹ÊÕÏÊäÈëÂ˲¨ÊÇ·ñʹÄÜ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg ENABLE: ʹÄܹÊÕÏÊäÈëÂ˲¨Æ÷
|
* @arg DISABLE: ʧÄܹÊÕÏÊäÈëÂ˲¨Æ÷
|
* @retval None
|
*/
|
void FTM_FaultPinFilterCmd(FTM_Type* FTMx, uint8_t FaultFilter, FunctionalState NewState)
|
{
|
uint32_t tempvalue;
|
|
tempvalue= ((uint32_t)0x10 << FaultFilter);
|
|
if (NewState != DISABLE)
|
{
|
/* Enable Fault input filter */
|
FTMx->FLTCTRL |= tempvalue;
|
}
|
else
|
{
|
/* Disable Fault input filter */
|
FTMx->FLTCTRL &= ~tempvalue;
|
}
|
}
|
|
|
/**
|
* @brief Ñ¡ÔñÂËÖµ´íÎóÊäÈë.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FilterValue:ÉèÖÃÂËÖµ 0x0~0xF.
|
* @retval None
|
*/
|
void FTM_SetFaultInFilter(FTM_Type* FTMx, uint32_t FilterValue)
|
{
|
FTMx->FLTCTRL &= ~FTM_FLTCTRL_FFVAL_MASK;
|
|
/* Selects the filter value */
|
FTMx->FLTCTRL |= (FilterValue << FTM_FLTCTRL_FFVAL_SHIFT);
|
}
|
|
|
/**
|
* @brief ÅäÖÃFTMÈ«¾ÖʱÖÓ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param NewState: Íⲿȫ¾Öʱ»ùÊÇ·ñʹÄÜ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg ENABLE: ʹÄÜÍⲿȫ¾Öʱ»ù
|
* @arg DISABLE: ʧÄÜÍⲿȫ¾Öʱ»ù
|
* @retval None
|
*/
|
void FTM_GTBEENCmd(FTM_Type* FTMx, FunctionalState NewState)
|
{
|
if (NewState != DISABLE)
|
{
|
/* Enable Use of an external global time base */
|
FTMx->CONF |= FTM_CONF_GTBEEN_MASK;
|
}
|
else
|
{
|
/* Disable Use of an external global time base */
|
FTMx->CONF &= ~FTM_CONF_GTBEEN_MASK;
|
}
|
}
|
|
|
/**
|
* @brief »ùÓÚÆäËüFTMsʹÄÜÈ«¾ÖʱÖÓ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param NewState: È«¾Öʱ»ùÐźÅÉú³ÉÊÇ·ñʹÄÜ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg ENABLE: ʹÄÜÈ«¾Öʱ»ùÐźÅÉú³É
|
* @arg DISABLE: ʧÄÜÈ«¾Öʱ»ùÐźÅÉú³É
|
* @retval None
|
*/
|
void FTM_GTBEOUTCmd(FTM_Type* FTMx, FunctionalState NewState)
|
{
|
if (NewState != DISABLE)
|
{
|
/* Enable A global time base signal generation */
|
FTMx->CONF |= FTM_CONF_GTBEOUT_MASK;
|
}
|
else
|
{
|
/* Disable A global time base signal generation */
|
FTMx->CONF &= ~FTM_CONF_GTBEOUT_MASK;
|
}
|
}
|
|
|
/**
|
* @brief ½øÈëDebugģʽ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param DebugMode£ºDebugModeÖµ 0~0x03.
|
* @retval None
|
*/
|
void FTM_SetDebugModeBehavior(FTM_Type* FTMx, uint32_t DebugMode)
|
{
|
FTMx->CONF &= ~FTM_CONF_BDMMODE_MASK;
|
|
/* Set the Debug Mode */
|
FTMx->CONF |= (DebugMode << FTM_CONF_BDMMODE_SHIFT);
|
}
|
|
/**
|
* @brief ¶¨Òå´íÎóÊäÈ뼫ÐÔ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FaultInput: Ö¸ÏòFTM_fault_polarity_filter_listÊý¾Ý.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_FAULTINPUT_FILTER0: ¹ÊÕÏÊäÈë0
|
* @arg FTM_FAULTINPUT_FILTER1: ¹ÊÕÏÊäÈë1
|
* @arg FTM_FAULTINPUT_FILTER2: ¹ÊÕÏÊäÈë2
|
* @arg FTM_FAULTINPUT_FILTER3: ¹ÊÕÏÊäÈë3
|
* @param polarity: ¹ÊÕÏÊäÈ뼫ÐÔ
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_FAULTINPOLARITY_HIGH: ¹ÊÕÏÊäÈ뼫ÐÔΪ¸ßµçƽÓÐЧ
|
* @arg FTM_FAULTINPOLARITY_LOW: ¹ÊÕÏÊäÈ뼫ÐÔΪµÍµçƽÓÐЧ
|
* @retval None
|
*/
|
void FTM_SetFaultInPolarity(FTM_Type* FTMx, uint8_t FaultInput, uint8_t polarity)
|
{
|
uint32_t polvalue;
|
|
polvalue = ((uint32_t)1<<FaultInput);
|
|
if (polarity != FTM_FAULTINPOLARITY_HIGH)
|
{
|
/* The fault input polarity is active low */
|
FTMx->FLTPOL |= polvalue;
|
}
|
else
|
{
|
/* The fault input polarity is active high */
|
FTMx->FLTPOL &= ~polvalue;
|
}
|
}
|
|
|
/**
|
* @brief ¿ØÖÆ×éºÏͨµÀ·×ª.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FTM_Channel: Ñ¡ÔñFTMͨµÀ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_INVERT_PAIRCHANNEL0: ͨµÀ×é0
|
* @arg FTM_INVERT_PAIRCHANNEL1: ͨµÀ×é1
|
* @arg FTM_INVERT_PAIRCHANNEL2: ͨµÀ×é2
|
* @arg FTM_INVERT_PAIRCHANNEL3: ͨµÀ×é3
|
* @param NewState:×éºÏͨµÀ·×ªÊÇ·ñʹÄÜ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg ENABLE: ×éºÏͨµÀ·×ªÊ¹ÄÜ
|
* @arg DISABLE: ×éºÏͨµÀ·×ª²»Ê¹ÄÜ
|
* @retval None
|
*/
|
void FTM_PairChannelsInvertCmd(FTM_Type* FTMx, uint8_t channelpair, FunctionalState NewState)
|
{
|
uint32_t tempvalue;
|
|
tempvalue= ((uint32_t)1<<channelpair);
|
|
if (NewState != DISABLE)
|
{
|
/* Enable Inverting */
|
FTMx->INVCTRL |= tempvalue;
|
}
|
else
|
{
|
/* Disable Inverting */
|
FTMx->INVCTRL &= ~tempvalue;
|
}
|
}
|
|
|
/**
|
* @brief Èí¼þÊä³ö¿ØÖÆͨµÀNÊÇ·ñʹÄÜ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FTM_Channel: Ñ¡ÔñFTMͨµÀ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_CHANNEL0: FTMxͨµÀ0
|
* @arg FTM_CHANNEL1: FTMxͨµÀ1
|
* @arg FTM_CHANNEL2: FTMxͨµÀ2
|
* @arg FTM_CHANNEL3: FTMxͨµÀ3
|
* @arg FTM_CHANNEL4: FTMxͨµÀ4
|
* @arg FTM_CHANNEL5: FTMxͨµÀ5
|
* @arg FTM_CHANNEL6: FTMxͨµÀ6
|
* @arg FTM_CHANNEL7: FTMxͨµÀ7
|
* @param NewState:ͨµÀNÈí¼þÊä³ö¿ØÖÆÊÇ·ñʹÄÜ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg ENABLE: ͨµÀNÈí¼þÊä³ö¿ØÖÆʹÄÜ
|
* @arg DISABLE: ͨµÀNÈí¼þÊä³ö¿ØÖÆʧÄÜ
|
* @retval None
|
*/
|
void FTM_SWOutControlCmd(FTM_Type* FTMx, uint8_t FTM_Channel, FunctionalState NewState)
|
{
|
uint32_t tempvalue;
|
tempvalue= ((uint32_t)1<<FTM_Channel);
|
|
if (NewState != DISABLE)
|
{
|
/* The channel output is affected */
|
FTMx->SWOCTRL |= tempvalue;
|
}
|
else
|
{
|
/* The channel output is not affected */
|
FTMx->SWOCTRL &= ~tempvalue;
|
}
|
}
|
|
/**
|
* @brief ÉèÖÃÈí¼þÊä³ö¿ØÖÆͨµÀNµÄÖµ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FTM_Channel: Ñ¡ÔñFTMͨµÀ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_CHANNEL0: FTMxͨµÀ0
|
* @arg FTM_CHANNEL1: FTMxͨµÀ1
|
* @arg FTM_CHANNEL2: FTMxͨµÀ2
|
* @arg FTM_CHANNEL3: FTMxͨµÀ3
|
* @arg FTM_CHANNEL4: FTMxͨµÀ4
|
* @arg FTM_CHANNEL5: FTMxͨµÀ5
|
* @arg FTM_CHANNEL6: FTMxͨµÀ6
|
* @arg FTM_CHANNEL7: FTMxͨµÀ7
|
* @param outvalue: ÉèÖÿØÖÆͨµÀNµÄÖµ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_SWCONTROL_OUT0: Èí¼þÊä³ö¿ØÖÆÇ¿ÖÆ0½øÈëͨµÀÊä³ö
|
* @arg FTM_SWCONTROL_OUT1: Èí¼þÊä³ö¿ØÖÆÇ¿ÖÆ1½øÈëͨµÀÊä³ö
|
|
* @retval None
|
*/
|
void FTM_SetSWOutControlValue(FTM_Type* FTMx, uint8_t FTM_Channel, uint8_t outvalue)
|
{
|
uint32_t tempvalue;
|
|
tempvalue= ((uint32_t)0x100<<FTM_Channel);
|
|
if (outvalue != FTM_SWCONTROL_OUT0)
|
{
|
/* The software output control forces 1 to the channel output */
|
FTMx->SWOCTRL |= tempvalue;
|
}
|
else
|
{
|
/* The software output control forces 0 to the channel output */
|
FTMx->SWOCTRL &= ~tempvalue;
|
}
|
}
|
|
|
/**
|
* @brief ÊÇ·ñ°üº¬Í¨µÀ±È½Ï½ø³Ì.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param Matchchannel: ÉèÖÃPWMLOAD¼Ä´æÆ÷ µÍ8λµÄÖµ.
|
* @retval None
|
*/
|
void FTM_SetLoadMatchChannels(FTM_Type* FTMx, uint32_t Matchchannel)
|
{
|
FTMx->PWMLOAD &= ~(uint32_t)0xFF ;
|
FTMx->PWMLOAD |= Matchchannel;
|
}
|
|
/**
|
* @brief ÊÇ·ñ°üº¬µ¥Í¨µÀ±È½Ï½ø³Ì.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FTM_Channel: Ñ¡ÔñFTMͨµÀ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_CHANNEL0: FTMxͨµÀ0
|
* @arg FTM_CHANNEL1: FTMxͨµÀ1
|
* @arg FTM_CHANNEL2: FTMxͨµÀ2
|
* @arg FTM_CHANNEL3: FTMxͨµÀ3
|
* @arg FTM_CHANNEL4: FTMxͨµÀ4
|
* @arg FTM_CHANNEL5: FTMxͨµÀ5
|
* @arg FTM_CHANNEL6: FTMxͨµÀ6
|
* @arg FTM_CHANNEL7: FTMxͨµÀ7
|
* @param include:ÊÇ·ñ°üº¬µ¥Í¨µÀ±È½Ï½ø³Ì
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM_CHANNELMATCH_NOTINCLUDE:²»°üº¬µ¥Í¨µÀ±È½Ï½ø³Ì
|
* @arg FTM_CHANNELMATCH_INCLUDE£º°üº¬µ¥Í¨µÀ±È½Ï½ø³Ì
|
* @retval None
|
*/
|
void FTM_SetLoadMatchChannel(FTM_Type* FTMx, uint8_t FTM_Channel, uint8_t include)
|
{
|
uint32_t tempvalue;
|
|
tempvalue= ((uint32_t)1<<FTM_Channel);
|
|
if (include != FTM_CHANNELMATCH_NOTINCLUDE)
|
{
|
/* Include the channel in the matching process */
|
FTMx->PWMLOAD |= tempvalue;
|
}
|
else
|
{
|
/* Do not include the channel in the matching process. */
|
FTMx->PWMLOAD &= ~tempvalue;
|
}
|
}
|
|
/**
|
* @brief ʹÄܼÓÔØMOD, CNTIN,CV¼Ä´æÆ÷µÄÖµ.
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param NewState:FTMx¼ÓÔØÊÇ·ñʹÄÜ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg ENABLE: ¼ÓÔØʹÄÜ
|
* @arg DISABLE: ¼ÓÔØʧÄÜ
|
* @retval None
|
*/
|
void FTM_SetLoadCmd(FTM_Type* FTMx, FunctionalState NewState)
|
{
|
if (NewState != DISABLE)
|
{
|
/* Enable Loading updated */
|
FTMx->PWMLOAD |= FTM_PWMLOAD_LDOK_MASK;
|
}
|
else
|
{
|
/* Disable Loading updated */
|
FTMx->PWMLOAD &= ~FTM_PWMLOAD_LDOK_MASK;
|
}
|
}
|
|
/**
|
* @brief ʹÄÜPWMͬ²½ºÍÖмä¼ÓÔØ
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param NewState:PWMͬ²½ºÍÖмä¼ÓÔØÊÇ·ñʹÄÜ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg ENABLE: ͬ²½ºÍÖмä¼ÓÔØʹÄÜ
|
* @arg DISABLE: ͬ²½ºÍÖмä¼ÓÔØʧÄÜ
|
* @retval None
|
*/
|
void FTM_SyncLoadEnable(FTM_Type* FTMx, FunctionalState NewState)
|
{
|
if (NewState != DISABLE)
|
{
|
FTMx->MODE |= FTM_MODE_SYNCLOADEN_MASK;
|
}
|
else
|
{
|
FTMx->MODE &= ~FTM_MODE_SYNCLOADEN_MASK;
|
}
|
}
|
|
|
/**
|
* @brief ¹ÊÕÏ¿ØÖÆʹÄÜ
|
* @param FTMx: Ñ¡ÔñFTMÍâÉè.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FTM0: FTM0ÍâÉè
|
* @arg FTM1: FTM1ÍâÉè
|
* @arg FTM2: FTM2ÍâÉè
|
* @param FaultControlChannel:¹ÊÕÏ¿ØÖÆͨµÀÑ¡Ôñ
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg FaultControlChanne0: ͨµÀ(0)ºÍ(1)ÖеĹÊÕÏ¿ØÖÆ
|
* @arg FaultControlChannel: ͨµÀ(2)ºÍ(3)ÖеĹÊÕÏ¿ØÖÆ
|
* @arg FaultControlChanne2: ͨµÀ(4)ºÍ(5)ÖеĹÊÕÏ¿ØÖÆ
|
* @arg FaultControlChanne3: ͨµÀ(6)ºÍ(7)ÖеĹÊÕÏ¿ØÖÆ
|
* @param NewState:¹ÊÕÏ¿ØÖÆÊÇ·ñʹÄÜ.
|
* Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
|
* @arg ENABLE: ¹ÊÕÏ¿ØÖÆʹÄÜ
|
* @arg DISABLE: ¹ÊÕÏ¿ØÖÆʧÄÜ
|
* @retval None
|
*/
|
void FTM_FaultControlEnable(FTM_Type* FTMx, uint32_t FaultControlChannel,FunctionalState NewState)
|
{
|
if (NewState != DISABLE)
|
{
|
FTMx->COMBINE |= FaultControlChannel;
|
}
|
else
|
{
|
FTMx->COMBINE &= ~FaultControlChannel;
|
}
|
}
|
|
|
/**
|
* @}
|
*/
|
|
/**
|
* @}
|
*/
|
|
/**
|
* @}
|
*/
|
#ifdef __cplusplus
|
}
|
#endif /* __cplusplus */
|
