/**
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******************************************************************************
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* @file xl_dma.h
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* @author software group
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* @brief This file contains all the functions prototypes for the DMA
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* firmware library.
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******************************************************************************
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* @attention
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*
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* 2019 by Chipways Communications,Inc. All Rights Reserved.
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* This software is supplied under the terms of a license
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* agreement or non-disclosure agreement with Chipways.
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* Passing on and copying of this document,and communication
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* of its contents is not permitted without prior written
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* authorization.
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*
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* <h2><center>© COPYRIGHT 2019 Chipways</center></h2>
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef XL_DMA_H_
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#define XL_DMA_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ---------------------------------------------------------------*/
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#include "XL6600.h"
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/* Register define ------------------------------------------------------------*/
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#define DMA_DMACTRLC_DBURSTC_MASK 0xE0000000u
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#define DMA_DMACTRLC_DBURSTC_SHIFT 29u
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#define DMA_DMACTRLC_SBURSTC_MASK 0x1C000000u
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#define DMA_DMACTRLC_SBURSTC_SHIFT 26u
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#define DMA_DMACTRLC_DWIDTHC_MASK 0x03000000u
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#define DMA_DMACTRLC_DWIDTHC_SHIFT 24u
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#define DMA_DMACTRLC_SWIDTHC_MASK 0x00C00000u
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#define DMA_DMACTRLC_SWIDTHC_SHIFT 22u
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#define DMA_DMACTRLC_TRANSIZEC_MASK 0x003FE000u
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#define DMA_DMACTRLC_TRANSIZEC_SHIFT 13u
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#define DMA_DMACTRLC_FLOWCTRLC_MASK 0x00001800u
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#define DMA_DMACTRLC_FLOWCTRLC_SHIFT 11u
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#define DMA_DMACTRLC_DSTPERC_MASK 0x00000780u
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#define DMA_DMACTRLC_DSTPERC_SHIFT 7u
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#define DMA_DMACTRLC_SRCPERC_MASK 0x00000078u
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#define DMA_DMACTRLC_SRCPERC_SHIFT 3u
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#define DMA_DMACTRLC_DSTINCC_MASK 0x00000004u
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#define DMA_DMACTRLC_DSTINCC_SHIFT 2u
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#define DMA_DMACTRLC_SRCINCC_MASK 0x00000002u
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#define DMA_DMACTRLC_SRCINCC_SHIFT 1u
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#define DMA_DMACTRLC_CHENC_MASK 0x00000001u
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#define DMA_DMACTRLC_CHENC_SHIFT 0u
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#define DMA_DMASTATUSC_TRANSLENGTH_MASK 0x0000007FEu
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#define DMA_DMASTATUSC_TRANSLENGTH_SHIFT 1u
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#define DMA_DMASTATUSC_BUSY_MASK 0x00000001u
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#define DMA_DMASTATUSC_BUSY_SHIFT 0u
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#define DMA_DMAEN_DMAEN_MASK 0x00000001u
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#define DMA_DMAEN_DMAEN_SHIFT 0u
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#define DMA_DMASRST_DMASRST_MASK 0x00000001u
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#define DMA_DMASRST_DMASRST_SHIFT 0u
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#define DMA_DMAINTSTATUS_INTCC3_MASK 0x00000080u
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#define DMA_DMAINTSTATUS_INTCC3_SHIFT 7u
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#define DMA_DMAINTSTATUS_INTCC2_MASK 0x00000040u
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#define DMA_DMAINTSTATUS_INTCC2_SHIFT 6u
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#define DMA_DMAINTSTATUS_INTCC1_MASK 0x00000020u
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#define DMA_DMAINTSTATUS_INTCC1_SHIFT 5u
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#define DMA_DMAINTSTATUS_INTCC0_MASK 0x00000010u
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#define DMA_DMAINTSTATUS_INTCC0_SHIFT 4u
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#define DMA_DMAINTSTATUS_INTERRC3_MASK 0x00000008u
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#define DMA_DMAINTSTATUS_INTERRC3_SHIFT 3u
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#define DMA_DMAINTSTATUS_INTERRC2_MASK 0x00000004u
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#define DMA_DMAINTSTATUS_INTERRC2_SHIFT 2u
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#define DMA_DMAINTSTATUS_INTERRC1_MASK 0x00000002u
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#define DMA_DMAINTSTATUS_INTERRC1_SHIFT 1u
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#define DMA_DMAINTSTATUS_INTERRC0_MASK 0x00000001u
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#define DMA_DMAINTSTATUS_INTERRC0_SHIFT 0u
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#define DMA_DMAINTMASK_MASKTCC3_MASK 0x00000080u
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#define DMA_DMAINTMASK_MASKTCC3_SHIFT 7u
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#define DMA_DMAINTMASK_MASKTCC2_MASK 0x00000040u
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#define DMA_DMAINTMASK_MASKTCC2_SHIFT 6u
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#define DMA_DMAINTMASK_MASKTCC1_MASK 0x00000020u
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#define DMA_DMAINTMASK_MASKTCC1_SHIFT 5u
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#define DMA_DMAINTMASK_MASKTCC0_MASK 0x00000010u
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#define DMA_DMAINTMASK_MASKTCC0_SHIFT 4u
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#define DMA_DMAINTMASK_MASKERRC3_MASK 0x00000008u
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#define DMA_DMAINTMASK_MASKERRC3_SHIFT 3u
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#define DMA_DMAINTMASK_MASKERRC2_MASK 0x00000004u
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#define DMA_DMAINTMASK_MASKERRC2_SHIFT 2u
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#define DMA_DMAINTMASK_MASKERRC1_MASK 0x00000002u
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#define DMA_DMAINTMASK_MASKERRC1_SHIFT 1u
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#define DMA_DMAINTMASK_MASKERRC0_MASK 0x00000001u
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#define DMA_DMAINTMASK_MASKERRC0_SHIFT 0u
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#define DMA_DMAPERREQ_ADCRXREQ_MASK 0x00000800u
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#define DMA_DMAPERREQ_ADCRXREQ_SHIFT 11u
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#define DMA_DMAPERREQ_ADCTXREQ_MASK 0x00000400u
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#define DMA_DMAPERREQ_ADCTXREQ_SHIFT 10u
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#define DMA_DMAPERREQ_UART2RXREQ_MASK 0x00000200u
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#define DMA_DMAPERREQ_UART2RXREQ_SHIFT 9u
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#define DMA_DMAPERREQ_UART2TXREQ_MASK 0x00000100u
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#define DMA_DMAPERREQ_UART2TXREQ_SHIFT 8u
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#define DMA_DMAPERREQ_UART1RXREQ_MASK 0x00000080u
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#define DMA_DMAPERREQ_UART1RXREQ_SHIFT 7u
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#define DMA_DMAPERREQ_UART1TXREQ_MASK 0x00000040u
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#define DMA_DMAPERREQ_UART1TXREQ_SHIFT 6u
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#define DMA_DMAPERREQ_UART0RXREQ_MASK 0x00000020u
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#define DMA_DMAPERREQ_UART0RXREQ_SHIFT 5u
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#define DMA_DMAPERREQ_UART0TXREQ_MASK 0x00000010u
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#define DMA_DMAPERREQ_UART0TXREQ_SHIFT 4u
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#define DMA_DMAPERREQ_SPI0RXREQ_MASK 0x00000008u
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#define DMA_DMAPERREQ_SPI0RXREQ_SHIFT 3u
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#define DMA_DMAPERREQ_SPI0TXREQ_MASK 0x00000004u
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#define DMA_DMAPERREQ_SPI0TXREQ_SHIFT 2u
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#define DMA_DMAPERREQ_SPI1RXREQ_MASK 0x00000002u
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#define DMA_DMAPERREQ_SPI1RXREQ_SHIFT 1u
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#define DMA_DMAPERREQ_SPI1TXREQ_MASK 0x00000001u
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#define DMA_DMAPERREQ_SPI1TXREQ_SHIFT 0u
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/** DMA - Register Layout Typedef */
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typedef struct{
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struct {
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__IO uint32_t DMASRCADDRC; /*!< ÐŵÀÔ´µØÖ·¼Ä´æÆ÷ */
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__IO uint32_t DMADSTADDRC; /*!< ͨµÀÄ¿µÄµØÖ·¼Ä´æÆ÷ */
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__IO uint32_t DMACTRLC; /*!< ͨµÀ¿ØÖƼĴæÆ÷ */
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__IO uint32_t DMASTATUSC; /*!< ͨµÀ״̬¼Ä´æÆ÷ */
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}DMACHANREG[4];
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__IO uint32_t DMAEN; /*!< DMA ʹÄܼĴæÆ÷ */
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__IO uint32_t DMASRST; /*!< DMA Èí¸´Î»¼Ä´æÆ÷ */
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__IO uint32_t DMAINTSTATUS; /*!< ÖжÏ״̬/ÖжÏÇå³ý¼Ä´æÆ÷ */
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__IO uint32_t DMAINTMASK; /*!< ÖжÏÆÁ±Î¼Ä´æÆ÷ */
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__I uint32_t DMAPERREQ; /*!< ÍâÉèÇëÇó״̬¼Ä´æÆ÷ */
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} DMA_Type;
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extern DMA_Type *DMA;
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/** @addtogroup XL6600_StdPeriph_Driver
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* @{
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*/
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/** @addtogroup DMA
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/**
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* @brief DMA³õʼ»¯½á¹¹Ì嶨Òå
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*/
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typedef struct
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{
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uint8_t chan; /*!< ÐŵÀ */
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uint8_t TargetBurst; /*!< ÉêÇëÒ»´Î×ÜÏߣ¬ÊÕµ½µÄÊý¾Ý */
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uint8_t SourceBurst; /*!< ÉêÇëÒ»´Î×ÜÏߣ¬·¢Ë͵ÄÊý¾Ý */
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uint8_t TargetWidth; /*!< Ä¿±êÒ»¸öÊý¾ÝµÄbit */
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uint8_t SourceWidth; /*!< Ô´Ò»¸öÊý¾ÝµÄbit */
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uint16_t TransferSize; /*!< ´«ÊäÊý¾ÝµÄ´óС */
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uint8_t FlowControl; /*!< Ä¿±êÉ豸ID */
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uint8_t TargetPerID; /*!< Ä¿±êÉ豸ID */
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uint8_t SourcePerID; /*!< Ô´É豸ID */
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uint8_t TargetAddrInc; /*!< Ä¿µÄµØÖ·µÝÔöʹÄÜλ */
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uint8_t SourceAddrInc; /*!< Ô´µØÖ·µÝÔöʹÄÜλ */
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}DMA_InitTypeDef;
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extern DMA_Type *DMA;
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup DMA_Exported_Constants DMAÄ£¿éʹÓòÎÊý¶¨Òå
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* @{
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*/
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/** @defgroup DMA_Channel_Num DMAͨµÀ
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* @{
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*/
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typedef enum
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{
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DMA_Channel_0 = 0, /*!< DMAͨµÀ0 */
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DMA_Channel_1 , /*!< DMAͨµÀ1 */
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DMA_Channel_2 , /*!< DMAͨµÀ2 */
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DMA_Channel_3 , /*!< DMAͨµÀ3 */
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}DMA_Channel_Num;
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/**
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* @}
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*/
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/** @defgroup DMA_TargetData_Burst DMAÄ¿µÄ²Ù×÷Êý¾ÝBurstÑ¡Ôñ
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* @{
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*/
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typedef enum
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{
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DMA_TargetBurst1 = 0, /*!< Ä¿µÄ²Ù×÷Êý¾ÝBurstΪ1 */
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DMA_TargetBurst2, /*!< Ä¿µÄ²Ù×÷Êý¾ÝBurstΪ2 */
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DMA_TargetBurst4, /*!< Ä¿µÄ²Ù×÷Êý¾ÝBurstΪ4 */
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DMA_TargetBurst8, /*!< Ä¿µÄ²Ù×÷Êý¾ÝBurstΪ8 */
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DMA_TargetBurst16, /*!< Ä¿µÄ²Ù×÷Êý¾ÝBurstΪ16 */
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DMA_TargetBurst32 /*!< Ä¿µÄ²Ù×÷Êý¾ÝBurstΪ32 */
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}DMA_TargetBurstDef;
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/**
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* @}
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*/
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/** @defgroup DMA_SourceData_Burst DMAÔ´²Ù×÷Êý¾ÝBurstÑ¡Ôñ
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* @{
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*/
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typedef enum
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{
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DMA_SourceBurst1 = 0, /*!< Ô´²Ù×÷Êý¾ÝBurstΪ1 */
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DMA_SourceBurst2, /*!< Ô´²Ù×÷Êý¾ÝBurstΪ2 */
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DMA_SourceBurst4, /*!< Ô´²Ù×÷Êý¾ÝBurstΪ4 */
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DMA_SourceBurst8, /*!< Ô´²Ù×÷Êý¾ÝBurstΪ8 */
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DMA_SourceBurst16, /*!< Ô´²Ù×÷Êý¾ÝBurstΪ16 */
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DMA_SourceBurst32 /*!< Ô´²Ù×÷Êý¾ÝBurstΪ32 */
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}DMA_SourceBurstDef;
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/**
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* @}
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*/
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/** @defgroup DMA_TargetData_Width DMAÄ¿µÄ²Ù×÷Êý¾Ýλ¿íÑ¡Ôñ
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* @{
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*/
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typedef enum
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{
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DMA_TargetWidth8 = 0, /*!< Ä¿±ê²Ù×÷Êý¾Ýλ¿í8λ */
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DMA_TargetWidth16, /*!< Ä¿±ê²Ù×÷Êý¾Ýλ¿í16λ */
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DMA_TargetWidth32, /*!< Ä¿±ê²Ù×÷Êý¾Ýλ¿í32λ */
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DMA_TargetWidth32_1, /*!< Ä¿±ê²Ù×÷Êý¾Ýλ¿í32λ */
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}DMA_TargetWidthDef;
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/**
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* @}
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*/
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/** @defgroup DMA_SourceData_Width DMAÔ´²Ù×÷Êý¾Ýλ¿íÑ¡Ôñ
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* @{
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*/
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typedef enum
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{
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DMA_SourceWidth8 = 0, /*!< Ô´²Ù×÷Êý¾Ýλ¿í8λ */
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DMA_SourceWidth16, /*!< Ô´²Ù×÷Êý¾Ýλ¿í16λ */
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DMA_SourceWidth32, /*!< Ô´²Ù×÷Êý¾Ýλ¿í32λ */
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DMA_SourceWidth32_1, /*!< Ô´²Ù×÷Êý¾Ýλ¿í32λ */
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}DMA_SourceWidthDef;
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/**
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* @}
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*/
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/** @defgroup DMA_Flow_Control DMA´«Ê䷽ʽѡÔñ
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* @{
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*/
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typedef enum
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{
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DMA_MemoryToMemory = 0, /*!< ´æ´¢Æ÷µ½´æ´¢Æ÷ */
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DMA_MemoryToPeripheral , /*!< ´æ´¢Æ÷µ½ÍâÉè */
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DMA_PeripheralToMemory , /*!< ÍâÉèµ½´æ´¢Æ÷ */
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DMA_PeripheralToPeripheral , /*!< ÍâÉèµ½ÍâÉè */
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}DMA_FlowControlDef;
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/**
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* @}
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*/
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/** @defgroup DMA_Peripheral_ID DMAÄ¿µÄÍâÉèIDÑ¡Ôñ
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* @{
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*/
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typedef enum
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{
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DMA_SPI1_Tx = 0,
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DMA_SPI1_Rx,
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DMA_SPI0_Tx,
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DMA_SPI0_Rx,
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DMA_UART0_Tx,
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DMA_UART0_Rx,
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DMA_UART1_Tx,
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DMA_UART1_Rx,
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DMA_UART2_Tx,
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DMA_UART2_Rx,
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DMA_ADC_Tx,
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DMA_ADC_Rx,
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DMA_Reserver0,
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DMA_Reserver1,
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DMA_Reserver2,
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DMA_Reserver3,
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}DMA_Peripheral_IDDef;
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/**
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* @}
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*/
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/** @defgroup DMA_Address_Add DMAµØÖ·×ÔÔö
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* @{
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*/
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typedef enum
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{
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DMA_AddressNoAdd = 0, /*!< µØÖ·±£³Ö²»±ä */
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DMA_AddressAdd , /*!< µØÖ·µÝÔö */
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}DMA_AddrIncDef;
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/**
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* @}
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*/
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/** @defgroup DMA_Interrupt_Status DMAÖжÏ״̬¼°Çå³ý
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* @{
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*/
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typedef enum
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{
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DMA_Channel0_Err = 0, /*!< DMAͨµÀ0´íÎóÖÐ¶Ï */
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DMA_Channel1_Err, /*!< DMAͨµÀ0´íÎóÖÐ¶Ï */
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DMA_Channel2_Err, /*!< DMAͨµÀ0´íÎóÖÐ¶Ï */
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DMA_Channel3_Err, /*!< DMAͨµÀ0´íÎóÖÐ¶Ï */
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DMA_Channel0_TransferFinish, /*!< DMAͨµÀ0´«ÊäÍê³ÉÖÐ¶Ï */
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DMA_Channel1_TransferFinish, /*!< DMAͨµÀ0´«ÊäÍê³ÉÖÐ¶Ï */
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DMA_Channel2_TransferFinish, /*!< DMAͨµÀ0´«ÊäÍê³ÉÖÐ¶Ï */
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DMA_Channel3_TransferFinish, /*!< DMAͨµÀ0´«ÊäÍê³ÉÖÐ¶Ï */
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DMA_ClearALL_Status = 0xFF /*!< Çå³ýËùÓÐDMAÖжÏ״̬ */
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}DMA_InterruptStatusDef;
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/**
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* @}
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*/
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/** @defgroup DMA_Interrupt_Mask DMAÖжÏÆÁ±Î
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* @{
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*/
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typedef enum
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{
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DMA_Channel0_Err_Mask = 0, /*!< DMAͨµÀ0´íÎóÖжÏÆÁ±Î */
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DMA_Channel1_Err_Mask, /*!< DMAͨµÀ1´íÎóÖжÏÆÁ±Î */
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DMA_Channel2_Err_Mask, /*!< DMAͨµÀ2´íÎóÖжÏÆÁ±Î */
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DMA_Channel3_Err_Mask, /*!< DMAͨµÀ3´íÎóÖжÏÆÁ±Î */
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DMA_Channel0_TransferFinish_Mask, /*!< DMAͨµÀ0´«ÊäÍê³ÉÖжÏÆÁ±Î */
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DMA_Channel1_TransferFinish_Mask, /*!< DMAͨµÀ1´«ÊäÍê³ÉÖжÏÆÁ±Î */
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DMA_Channel2_TransferFinish_Mask, /*!< DMAͨµÀ2´«ÊäÍê³ÉÖжÏÆÁ±Î */
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DMA_Channel3_TransferFinish_Mask, /*!< DMAͨµÀ3´«ÊäÍê³ÉÖжÏÆÁ±Î */
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}DMA_InterruptMaskDef;
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/**
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* @}
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*/
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/** @defgroup DMA_Peripheral_ResquestDef DMAÍâÉèÇëÇó״̬
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* @{
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*/
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typedef enum
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{
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DMA_SPI1_Tx_Req = 0,
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DMA_SPI1_Rx_Req,
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DMA_SPI0_Tx_Req,
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DMA_SPI0_Rx_Req,
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DMA_UART0_Tx_Req,
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DMA_UART0_Rx_Req,
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DMA_UART1_Tx_Req,
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DMA_UART1_Rx_Req,
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DMA_UART2_Tx_Req,
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DMA_UART2_Rx_Req,
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DMA_ADC_Tx_Req,
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DMA_ADC_Rx_Req,
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}DMA_Peripheral_ResquestDef;
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/**
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* @}
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*/
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/** @defgroup DMA_Chan_Status DMAͨµÀ״̬
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* @{
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*/
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typedef enum
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{
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DMA_Chan_Idle = 0, /*!< DMAͨµÀ¿ÕÏÐ */
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DMA_Chan_Busy /*!< DMAͨµÀæ */
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}DMA_Chan_Status;
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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void DMA_ChannelInit(const DMA_InitTypeDef *DMA_InitStruct);
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void DMA_Enable(FunctionalState NewState);
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void DMA_ChannelEnableCmd(uint8_t Channel,FunctionalState NewState);
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void DMA_SetSourceAddress(uint8_t Channel,uint32_t address);
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void DMA_SetTargetAddress(uint8_t Channel,uint32_t address);
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void DMA_SetTransferSize(uint8_t channel,uint16_t len);
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uint8_t DMA_GetChannelStatus(uint8_t Channel);
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uint16_t DMA_GetChanTransferDataLen(uint8_t Channel);
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uint8_t DMA_GetInterruptStatus(uint8_t DMA_InterruptStatusType);
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void DMA_ClearInterruptStatus(const uint8_t DMA_InterruptStatusType);
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void DMA_InterruptEnable(uint8_t DMA_InterruptMaskType,FunctionalState NewState);
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uint32_t DMA_GetPeripheralResquestStatus(const uint8_t DMA_Peripheral_ResquestType);
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#ifdef __cplusplus
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}
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#endif
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#endif
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/**
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* @}
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*/
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/**
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* @}
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*/
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