/**
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******************************************************************************
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* @file xl_ftm.h
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* @author software group
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* @brief This file contains all the functions prototypes for the FTM
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* firmware library.
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******************************************************************************
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* @attention
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*
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* 2019 by Chipways Communications,Inc. All Rights Reserved.
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* This software is supplied under the terms of a license
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* agreement or non-disclosure agreement with Chipways.
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* Passing on and copying of this document,and communication
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* of its contents is not permitted without prior written
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* authorization.
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*
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* <h2><center>© COPYRIGHT 2019 Chipways</center></h2>
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef XL_FTM_H__
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#define XL_FTM_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ---------------------------------------------------------------*/
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#include <XL6600.h>
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/* Register define ------------------------------------------------------------*/
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/* SC Bit Fields */
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#define FTM_SC_PS_MASK 0x7u
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#define FTM_SC_PS_SHIFT 0
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#define FTM_SC_CLKS_MASK 0x18u
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#define FTM_SC_CLKS_SHIFT 3
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#define FTM_SC_CPWMS_MASK 0x20u
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#define FTM_SC_CPWMS_SHIFT 5
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#define FTM_SC_TOIE_MASK 0x40u
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#define FTM_SC_TOIE_SHIFT 6
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#define FTM_SC_TOF_MASK 0x80u
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#define FTM_SC_TOF_SHIFT 7
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/* CNT Bit Fields */
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#define FTM_CNT_COUNT_MASK 0xFFFFu
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#define FTM_CNT_COUNT_SHIFT 0
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/* MOD Bit Fields */
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#define FTM_MOD_MOD_MASK 0xFFFFu
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#define FTM_MOD_MOD_SHIFT 0
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/* CnSC Bit Fields */
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#define FTM_CnSC_ELSA_MASK 0x4u
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#define FTM_CnSC_ELSA_SHIFT 2
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#define FTM_CnSC_ELSB_MASK 0x8u
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#define FTM_CnSC_ELSB_SHIFT 3
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#define FTM_CnSC_MSA_MASK 0x10u
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#define FTM_CnSC_MSA_SHIFT 4
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#define FTM_CnSC_MSB_MASK 0x20u
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#define FTM_CnSC_MSB_SHIFT 5
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#define FTM_CnSC_CHIE_MASK 0x40u
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#define FTM_CnSC_CHIE_SHIFT 6
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#define FTM_CnSC_CHF_MASK 0x80u
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#define FTM_CnSC_CHF_SHIFT 7
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/* CnV Bit Fields */
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#define FTM_CnV_VAL_MASK 0xFFFFu
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#define FTM_CnV_VAL_SHIFT 0
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/* CNTIN Bit Fields */
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#define FTM_CNTIN_INIT_MASK 0xFFFFu
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#define FTM_CNTIN_INIT_SHIFT 0
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/* STATUS Bit Fields */
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#define FTM_STATUS_CH0F_MASK 0x1u
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#define FTM_STATUS_CH0F_SHIFT 0
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#define FTM_STATUS_CH1F_MASK 0x2u
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#define FTM_STATUS_CH1F_SHIFT 1
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#define FTM_STATUS_CH2F_MASK 0x4u
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#define FTM_STATUS_CH2F_SHIFT 2
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#define FTM_STATUS_CH3F_MASK 0x8u
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#define FTM_STATUS_CH3F_SHIFT 3
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#define FTM_STATUS_CH4F_MASK 0x10u
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#define FTM_STATUS_CH4F_SHIFT 4
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#define FTM_STATUS_CH5F_MASK 0x20u
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#define FTM_STATUS_CH5F_SHIFT 5
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#define FTM_STATUS_CH6F_MASK 0x40u
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#define FTM_STATUS_CH6F_SHIFT 6
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#define FTM_STATUS_CH7F_MASK 0x80u
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#define FTM_STATUS_CH7F_SHIFT 7
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/* MODE Bit Fields */
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#define FTM_MODE_SYNCLOADEN_MASK 0x1u
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#define FTM_MODE_SYNCLOADEN_SHIFT 0
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#define FTM_MODE_INIT_MASK 0x2u
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#define FTM_MODE_INIT_SHIFT 1
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#define FTM_MODE_WPDIS_MASK 0x4u
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#define FTM_MODE_WPDIS_SHIFT 2
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#define FTM_MODE_PWMSYNC_MASK 0x8u
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#define FTM_MODE_PWMSYNC_SHIFT 3
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#define FTM_MODE_CAPTEST_MASK 0x10u
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#define FTM_MODE_CAPTEST_SHIFT 4
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#define FTM_MODE_FAULTM_MASK 0x60u
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#define FTM_MODE_FAULTM_SHIFT 5
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#define FTM_MODE_FAULTIE_MASK 0x80u
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#define FTM_MODE_FAULTIE_SHIFT 7
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/* SYNC Bit Fields */
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#define FTM_SYNC_CNTMIN_MASK 0x1u
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#define FTM_SYNC_CNTMIN_SHIFT 0
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#define FTM_SYNC_CNTMAX_MASK 0x2u
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#define FTM_SYNC_CNTMAX_SHIFT 1
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#define FTM_SYNC_REINIT_MASK 0x4u
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#define FTM_SYNC_REINIT_SHIFT 2
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#define FTM_SYNC_SYNCHOM_MASK 0x8u
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#define FTM_SYNC_SYNCHOM_SHIFT 3
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#define FTM_SYNC_TRIG0_MASK 0x10u
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#define FTM_SYNC_TRIG0_SHIFT 4
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#define FTM_SYNC_TRIG1_MASK 0x20u
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#define FTM_SYNC_TRIG1_SHIFT 5
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#define FTM_SYNC_TRIG2_MASK 0x40u
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#define FTM_SYNC_TRIG2_SHIFT 6
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#define FTM_SYNC_SWSYNC_MASK 0x80u
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#define FTM_SYNC_SWSYNC_SHIFT 7
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/* OUTINIT Bit Fields */
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#define FTM_OUTINIT_CH0OI_MASK 0x1u
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#define FTM_OUTINIT_CH0OI_SHIFT 0
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#define FTM_OUTINIT_CH1OI_MASK 0x2u
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#define FTM_OUTINIT_CH1OI_SHIFT 1
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#define FTM_OUTINIT_CH2OI_MASK 0x4u
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#define FTM_OUTINIT_CH2OI_SHIFT 2
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#define FTM_OUTINIT_CH3OI_MASK 0x8u
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#define FTM_OUTINIT_CH3OI_SHIFT 3
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#define FTM_OUTINIT_CH4OI_MASK 0x10u
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#define FTM_OUTINIT_CH4OI_SHIFT 4
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#define FTM_OUTINIT_CH5OI_MASK 0x20u
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#define FTM_OUTINIT_CH5OI_SHIFT 5
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#define FTM_OUTINIT_CH6OI_MASK 0x40u
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#define FTM_OUTINIT_CH6OI_SHIFT 6
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#define FTM_OUTINIT_CH7OI_MASK 0x80u
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#define FTM_OUTINIT_CH7OI_SHIFT 7
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/* OUTMASK Bit Fields */
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#define FTM_OUTMASK_CH0OM_MASK 0x1u
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#define FTM_OUTMASK_CH0OM_SHIFT 0
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#define FTM_OUTMASK_CH1OM_MASK 0x2u
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#define FTM_OUTMASK_CH1OM_SHIFT 1
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#define FTM_OUTMASK_CH2OM_MASK 0x4u
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#define FTM_OUTMASK_CH2OM_SHIFT 2
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#define FTM_OUTMASK_CH3OM_MASK 0x8u
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#define FTM_OUTMASK_CH3OM_SHIFT 3
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#define FTM_OUTMASK_CH4OM_MASK 0x10u
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#define FTM_OUTMASK_CH4OM_SHIFT 4
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#define FTM_OUTMASK_CH5OM_MASK 0x20u
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#define FTM_OUTMASK_CH5OM_SHIFT 5
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#define FTM_OUTMASK_CH6OM_MASK 0x40u
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#define FTM_OUTMASK_CH6OM_SHIFT 6
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#define FTM_OUTMASK_CH7OM_MASK 0x80u
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#define FTM_OUTMASK_CH7OM_SHIFT 7
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/* COMBINE Bit Fields */
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#define FTM_COMBINE_COMBINE0_MASK 0x1u
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#define FTM_COMBINE_COMBINE0_SHIFT 0
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#define FTM_COMBINE_COMP0_MASK 0x2u
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#define FTM_COMBINE_COMP0_SHIFT 1
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#define FTM_COMBINE_DECAPEN0_MASK 0x4u
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#define FTM_COMBINE_DECAPEN0_SHIFT 2
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#define FTM_COMBINE_DECAP0_MASK 0x8u
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#define FTM_COMBINE_DECAP0_SHIFT 3
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#define FTM_COMBINE_DTEN0_MASK 0x10u
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#define FTM_COMBINE_DTEN0_SHIFT 4
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#define FTM_COMBINE_SYNCEN0_MASK 0x20u
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#define FTM_COMBINE_SYNCEN0_SHIFT 5
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#define FTM_COMBINE_FAULTEN0_MASK 0x40u
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#define FTM_COMBINE_FAULTEN0_SHIFT 6
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#define FTM_COMBINE_COMBINE1_MASK 0x100u
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#define FTM_COMBINE_COMBINE1_SHIFT 8
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#define FTM_COMBINE_COMP1_MASK 0x200u
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#define FTM_COMBINE_COMP1_SHIFT 9
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#define FTM_COMBINE_DECAPEN1_MASK 0x400u
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#define FTM_COMBINE_DECAPEN1_SHIFT 10
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#define FTM_COMBINE_DECAP1_MASK 0x800u
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#define FTM_COMBINE_DECAP1_SHIFT 11
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#define FTM_COMBINE_DTEN1_MASK 0x1000u
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#define FTM_COMBINE_DTEN1_SHIFT 12
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#define FTM_COMBINE_SYNCEN1_MASK 0x2000u
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#define FTM_COMBINE_SYNCEN1_SHIFT 13
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#define FTM_COMBINE_FAULTEN1_MASK 0x4000u
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#define FTM_COMBINE_FAULTEN1_SHIFT 14
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#define FTM_COMBINE_COMBINE2_MASK 0x10000u
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#define FTM_COMBINE_COMBINE2_SHIFT 16
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#define FTM_COMBINE_COMP2_MASK 0x20000u
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#define FTM_COMBINE_COMP2_SHIFT 17
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#define FTM_COMBINE_DECAPEN2_MASK 0x40000u
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#define FTM_COMBINE_DECAPEN2_SHIFT 18
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#define FTM_COMBINE_DECAP2_MASK 0x80000u
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#define FTM_COMBINE_DECAP2_SHIFT 19
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#define FTM_COMBINE_DTEN2_MASK 0x100000u
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#define FTM_COMBINE_DTEN2_SHIFT 20
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#define FTM_COMBINE_SYNCEN2_MASK 0x200000u
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#define FTM_COMBINE_SYNCEN2_SHIFT 21
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#define FTM_COMBINE_FAULTEN2_MASK 0x400000u
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#define FTM_COMBINE_FAULTEN2_SHIFT 22
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#define FTM_COMBINE_COMBINE3_MASK 0x1000000u
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#define FTM_COMBINE_COMBINE3_SHIFT 24
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#define FTM_COMBINE_COMP3_MASK 0x2000000u
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#define FTM_COMBINE_COMP3_SHIFT 25
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#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
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#define FTM_COMBINE_DECAPEN3_SHIFT 26
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#define FTM_COMBINE_DECAP3_MASK 0x8000000u
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#define FTM_COMBINE_DECAP3_SHIFT 27
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#define FTM_COMBINE_DTEN3_MASK 0x10000000u
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#define FTM_COMBINE_DTEN3_SHIFT 28
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#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
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#define FTM_COMBINE_SYNCEN3_SHIFT 29
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#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
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#define FTM_COMBINE_FAULTEN3_SHIFT 30
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/* DEADTIME Bit Fields */
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#define FTM_DEADTIME_DTVAL_MASK 0x3Fu
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#define FTM_DEADTIME_DTVAL_SHIFT 0
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#define FTM_DEADTIME_DTPS_MASK 0xC0u
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#define FTM_DEADTIME_DTPS_SHIFT 6
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/* EXTTRIG Bit Fields */
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#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
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#define FTM_EXTTRIG_CH2TRIG_SHIFT 0
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#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
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#define FTM_EXTTRIG_CH3TRIG_SHIFT 1
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#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
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#define FTM_EXTTRIG_CH4TRIG_SHIFT 2
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#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
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#define FTM_EXTTRIG_CH5TRIG_SHIFT 3
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#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
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#define FTM_EXTTRIG_CH0TRIG_SHIFT 4
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#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
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#define FTM_EXTTRIG_CH1TRIG_SHIFT 5
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#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
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#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
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#define FTM_EXTTRIG_TRIGF_MASK 0x80u
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#define FTM_EXTTRIG_TRIGF_SHIFT 7
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/* POL Bit Fields */
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#define FTM_POL_POL0_MASK 0x1u
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#define FTM_POL_POL0_SHIFT 0
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#define FTM_POL_POL1_MASK 0x2u
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#define FTM_POL_POL1_SHIFT 1
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#define FTM_POL_POL2_MASK 0x4u
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#define FTM_POL_POL2_SHIFT 2
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#define FTM_POL_POL3_MASK 0x8u
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#define FTM_POL_POL3_SHIFT 3
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#define FTM_POL_POL4_MASK 0x10u
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#define FTM_POL_POL4_SHIFT 4
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#define FTM_POL_POL5_MASK 0x20u
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#define FTM_POL_POL5_SHIFT 5
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#define FTM_POL_POL6_MASK 0x40u
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#define FTM_POL_POL6_SHIFT 6
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#define FTM_POL_POL7_MASK 0x80u
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#define FTM_POL_POL7_SHIFT 7
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/* FMS Bit Fields */
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#define FTM_FMS_FAULTF0_MASK 0x1u
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#define FTM_FMS_FAULTF0_SHIFT 0
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#define FTM_FMS_FAULTF1_MASK 0x2u
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#define FTM_FMS_FAULTF1_SHIFT 1
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#define FTM_FMS_FAULTF2_MASK 0x4u
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#define FTM_FMS_FAULTF2_SHIFT 2
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#define FTM_FMS_FAULTF3_MASK 0x8u
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#define FTM_FMS_FAULTF3_SHIFT 3
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#define FTM_FMS_FAULTIN_MASK 0x20u
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#define FTM_FMS_FAULTIN_SHIFT 5
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#define FTM_FMS_WPEN_MASK 0x40u
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#define FTM_FMS_WPEN_SHIFT 6
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#define FTM_FMS_FAULTF_MASK 0x80u
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#define FTM_FMS_FAULTF_SHIFT 7
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/* FILTER Bit Fields */
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#define FTM_FILTER_CH0FVAL_MASK 0xFu
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#define FTM_FILTER_CH0FVAL_SHIFT 0
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#define FTM_FILTER_CH1FVAL_MASK 0xF0u
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#define FTM_FILTER_CH1FVAL_SHIFT 4
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#define FTM_FILTER_CH2FVAL_MASK 0xF00u
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#define FTM_FILTER_CH2FVAL_SHIFT 8
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#define FTM_FILTER_CH3FVAL_MASK 0xF000u
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#define FTM_FILTER_CH3FVAL_SHIFT 12
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/* FLTCTRL Bit Fields */
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#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
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#define FTM_FLTCTRL_FAULT0EN_SHIFT 0
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#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
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#define FTM_FLTCTRL_FAULT1EN_SHIFT 1
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#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
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#define FTM_FLTCTRL_FAULT2EN_SHIFT 2
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#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
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#define FTM_FLTCTRL_FAULT3EN_SHIFT 3
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#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
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#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
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#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
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#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
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#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
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#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
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#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
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#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
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#define FTM_FLTCTRL_FFVAL_MASK 0xF00u
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#define FTM_FLTCTRL_FFVAL_SHIFT 8
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/* CONF Bit Fields */
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#define FTM_CONF_NUMTOF_MASK 0x1Fu
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#define FTM_CONF_NUMTOF_SHIFT 0
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#define FTM_CONF_BDMMODE_MASK 0xC0u
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#define FTM_CONF_BDMMODE_SHIFT 6
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#define FTM_CONF_GTBEEN_MASK 0x200u
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#define FTM_CONF_GTBEEN_SHIFT 9
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#define FTM_CONF_GTBEOUT_MASK 0x400u
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#define FTM_CONF_GTBEOUT_SHIFT 10
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/* FLTPOL Bit Fields */
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#define FTM_FLTPOL_FLT0POL_MASK 0x1u
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#define FTM_FLTPOL_FLT0POL_SHIFT 0
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#define FTM_FLTPOL_FLT1POL_MASK 0x2u
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#define FTM_FLTPOL_FLT1POL_SHIFT 1
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#define FTM_FLTPOL_FLT2POL_MASK 0x4u
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#define FTM_FLTPOL_FLT2POL_SHIFT 2
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#define FTM_FLTPOL_FLT3POL_MASK 0x8u
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#define FTM_FLTPOL_FLT3POL_SHIFT 3
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/* SYNCONF Bit Fields */
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#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
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#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
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#define FTM_SYNCONF_CNTINC_MASK 0x4u
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#define FTM_SYNCONF_CNTINC_SHIFT 2
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#define FTM_SYNCONF_INVC_MASK 0x10u
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#define FTM_SYNCONF_INVC_SHIFT 4
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#define FTM_SYNCONF_SWOC_MASK 0x20u
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#define FTM_SYNCONF_SWOC_SHIFT 5
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#define FTM_SYNCONF_SYNCMODE_MASK 0x80u
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#define FTM_SYNCONF_SYNCMODE_SHIFT 7
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#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
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#define FTM_SYNCONF_SWRSTCNT_SHIFT 8
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#define FTM_SYNCONF_SWWRBUF_MASK 0x200u
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#define FTM_SYNCONF_SWWRBUF_SHIFT 9
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#define FTM_SYNCONF_SWOM_MASK 0x400u
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#define FTM_SYNCONF_SWOM_SHIFT 10
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#define FTM_SYNCONF_SWINVC_MASK 0x800u
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#define FTM_SYNCONF_SWINVC_SHIFT 11
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#define FTM_SYNCONF_SWSOC_MASK 0x1000u
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#define FTM_SYNCONF_SWSOC_SHIFT 12
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#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
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#define FTM_SYNCONF_HWRSTCNT_SHIFT 16
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#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
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#define FTM_SYNCONF_HWWRBUF_SHIFT 17
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#define FTM_SYNCONF_HWOM_MASK 0x40000u
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#define FTM_SYNCONF_HWOM_SHIFT 18
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#define FTM_SYNCONF_HWINVC_MASK 0x80000u
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#define FTM_SYNCONF_HWINVC_SHIFT 19
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#define FTM_SYNCONF_HWSOC_MASK 0x100000u
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#define FTM_SYNCONF_HWSOC_SHIFT 20
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/* INVCTRL Bit Fields */
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#define FTM_INVCTRL_INV0EN_MASK 0x1u
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#define FTM_INVCTRL_INV0EN_SHIFT 0
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#define FTM_INVCTRL_INV1EN_MASK 0x2u
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#define FTM_INVCTRL_INV1EN_SHIFT 1
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#define FTM_INVCTRL_INV2EN_MASK 0x4u
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#define FTM_INVCTRL_INV2EN_SHIFT 2
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#define FTM_INVCTRL_INV3EN_MASK 0x8u
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#define FTM_INVCTRL_INV3EN_SHIFT 3
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/* SWOCTRL Bit Fields */
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#define FTM_SWOCTRL_CH0OC_MASK 0x1u
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#define FTM_SWOCTRL_CH0OC_SHIFT 0
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#define FTM_SWOCTRL_CH1OC_MASK 0x2u
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#define FTM_SWOCTRL_CH1OC_SHIFT 1
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#define FTM_SWOCTRL_CH2OC_MASK 0x4u
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#define FTM_SWOCTRL_CH2OC_SHIFT 2
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#define FTM_SWOCTRL_CH3OC_MASK 0x8u
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#define FTM_SWOCTRL_CH3OC_SHIFT 3
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#define FTM_SWOCTRL_CH4OC_MASK 0x10u
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#define FTM_SWOCTRL_CH4OC_SHIFT 4
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#define FTM_SWOCTRL_CH5OC_MASK 0x20u
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#define FTM_SWOCTRL_CH5OC_SHIFT 5
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#define FTM_SWOCTRL_CH6OC_MASK 0x40u
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#define FTM_SWOCTRL_CH6OC_SHIFT 6
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#define FTM_SWOCTRL_CH7OC_MASK 0x80u
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#define FTM_SWOCTRL_CH7OC_SHIFT 7
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#define FTM_SWOCTRL_CH0OCV_MASK 0x100u
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#define FTM_SWOCTRL_CH0OCV_SHIFT 8
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#define FTM_SWOCTRL_CH1OCV_MASK 0x200u
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#define FTM_SWOCTRL_CH1OCV_SHIFT 9
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#define FTM_SWOCTRL_CH2OCV_MASK 0x400u
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#define FTM_SWOCTRL_CH2OCV_SHIFT 10
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#define FTM_SWOCTRL_CH3OCV_MASK 0x800u
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#define FTM_SWOCTRL_CH3OCV_SHIFT 11
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#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
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#define FTM_SWOCTRL_CH4OCV_SHIFT 12
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#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
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#define FTM_SWOCTRL_CH5OCV_SHIFT 13
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#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
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#define FTM_SWOCTRL_CH6OCV_SHIFT 14
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#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
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#define FTM_SWOCTRL_CH7OCV_SHIFT 15
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/* PWMLOAD Bit Fields */
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#define FTM_PWMLOAD_CH0SEL_MASK 0x1u
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#define FTM_PWMLOAD_CH0SEL_SHIFT 0
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#define FTM_PWMLOAD_CH1SEL_MASK 0x2u
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#define FTM_PWMLOAD_CH1SEL_SHIFT 1
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#define FTM_PWMLOAD_CH2SEL_MASK 0x4u
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#define FTM_PWMLOAD_CH2SEL_SHIFT 2
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#define FTM_PWMLOAD_CH3SEL_MASK 0x8u
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#define FTM_PWMLOAD_CH3SEL_SHIFT 3
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#define FTM_PWMLOAD_CH4SEL_MASK 0x10u
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#define FTM_PWMLOAD_CH4SEL_SHIFT 4
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#define FTM_PWMLOAD_CH5SEL_MASK 0x20u
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#define FTM_PWMLOAD_CH5SEL_SHIFT 5
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#define FTM_PWMLOAD_CH6SEL_MASK 0x40u
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#define FTM_PWMLOAD_CH6SEL_SHIFT 6
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#define FTM_PWMLOAD_CH7SEL_MASK 0x80u
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#define FTM_PWMLOAD_CH7SEL_SHIFT 7
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#define FTM_PWMLOAD_LDOK_MASK 0x200u
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#define FTM_PWMLOAD_LDOK_SHIFT 9
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/** FTM - Register Layout Typedef */
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typedef struct {
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__IO uint32_t SC; /*!< ״̬ºÍ¿ØÖƼĴæÆ÷, offset: 0x0 */
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__IO uint32_t CNT; /*!< ¼ÆÊý¼Ä´æÆ÷, offset: 0x4 */
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__IO uint32_t MOD; /*!< Ä£Êý¼Ä´æÆ÷, offset: 0x8 */
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struct {
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__IO uint32_t CnSC; /*!< ͨµÀ״̬ºÍ¿ØÖƼĴæÆ÷, array offset: 0xC, array step: 0x8 */
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__IO uint32_t CnV; /*!< ͨµÀÖµ¼Ä´æÆ÷, array offset: 0x10, array step: 0x8 */
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} CONTROLS[8];
|
__IO uint32_t CNTIN; /*!< ¼ÆÊýÆ÷³õʼֵ¼Ä´æÆ÷, offset: 0x4C */
|
__IO uint32_t STATUS; /*!< ²¶×½ºÍ±È½Ï״̬¼Ä´æÆ÷, offset: 0x50 */
|
__IO uint32_t MODE; /*!< ÌØÐÔģʽѡÔñ¼Ä´æÆ÷, offset: 0x54 */
|
__IO uint32_t SYNC; /*!< ͬ²½¼Ä´æÆ÷, offset: 0x58 */
|
__IO uint32_t OUTINIT; /*!< ͨµÀÊä³öµÄ³õʼ״̬¼Ä´æÆ÷, offset: 0x5C */
|
__IO uint32_t OUTMASK; /*!< Êä³öÆÁ±Î¼Ä´æÆ÷, offset: 0x60 */
|
__IO uint32_t COMBINE; /*!< ÒÑÁ¬½ÓÐŵÀ¹¦ÄܼĴæÆ÷, offset: 0x64 */
|
__IO uint32_t DEADTIME; /*!< ËÀÇøʱ¼ä²åÈë¿ØÖÆ, offset: 0x68 */
|
__IO uint32_t EXTTRIG; /*!< FTMÍⲿ´¥·¢¼Ä´æÆ÷, offset: 0x6C */
|
__IO uint32_t POL; /*!< ͨµÀ¼«ÐԼĴæÆ÷, offset: 0x70 */
|
__IO uint32_t FMS; /*!< ¹ÊÕÏģʽ״̬¼Ä´æÆ÷, offset: 0x74 */
|
__IO uint32_t FILTER; /*!< ÊäÈ벶׽Â˲¨Æ÷¿ØÖƼĴæÆ÷, offset: 0x78 */
|
__IO uint32_t FLTCTRL; /*!< ¹ÊÕÏ¿ØÖƼĴæÆ÷, offset: 0x7C */
|
uint8_t RESERVED_1[4];
|
__IO uint32_t CONF; /*!< ÅäÖüĴæÆ÷, offset: 0x84 */
|
__IO uint32_t FLTPOL; /*!< FTM ¹ÊÕÏÊäÈ뼫ÐԼĴæÆ÷, offset: 0x88 */
|
__IO uint32_t SYNCONF; /*!< FTM Èí¼þÊä³ö¿ØÖƼĴæÆ÷, offset: 0x8C */
|
__IO uint32_t INVCTRL; /*!< FTM Èí¼þÊä³ö¿ØÖƼĴæÆ÷, offset: 0x90 */
|
__IO uint32_t SWOCTRL; /*!< FTM Èí¼þÊä³ö¿ØÖƼĴæÆ÷, offset: 0x94 */
|
__IO uint32_t PWMLOAD; /*!< FTM PWM ¼ÓÔؼĴæÆ÷, offset: 0x98 */
|
} FTM_Type, *FTM_MemMapPtr;
|
extern FTM_Type* FTM0;
|
extern FTM_Type* FTM1;
|
extern FTM_Type* FTM2;
|
|
|
/** @addtogroup XL6600_StdPeriph_Driver
|
* @{
|
*/
|
|
/** @addtogroup FTM
|
* @{
|
*/
|
|
/* Exported types ------------------------------------------------------------*/
|
|
/**
|
* @brief FTM ʱÖÓ³õʼ»¯½á¹¹Ìå
|
*/
|
typedef struct
|
{
|
uint32_t FTM_ClkSource; /*!< ʱÖÓÔ´ */
|
uint32_t FTM_Prescaler; /*!< ʱÖÓÔ¤·ÖƵϵÊý */
|
|
}FTM_InitTypeDef, *FTM_InitConfigPtr;
|
|
/**
|
* @brief FTM ×éºÏģʽ³õʼ»¯½á¹¹Ì嶨Òå
|
*/
|
typedef struct
|
{
|
uint32_t FTM_ChannelPair; /*!< ͨµÀ¶Ô */
|
uint32_t PWMEdgeSelect; /*!< PWM±ßÑØÑ¡Ôñ */
|
uint32_t FTM_CombineEn; /*!< ×éºÏͨµÀʹÄÜ */
|
uint32_t FTM_CompEn; /*!< ͨµÀ»¥²¹Ê¹ÄÜ */
|
uint32_t FTM_DeadtimeEn; /*!< ËÀÇøʱ¼äʹÄÜ */
|
uint32_t FTM_SynchronizationEn; /*!< ʹÄܼĴæÆ÷C(n)V ºÍC(n+1)VµÄPWMͬ²½ */
|
uint32_t FTM_FaultControlEn; /*!< ¹ÊÕÏ¿ØÖÆʹÄÜ */
|
|
}FTM_CombinePWMTypeDef, *FTM_CombinePWMConfigPtr;
|
|
/**
|
* @brief FTM ±È½Ï¹¦Äܳõʼ»¯½á¹¹Ìå
|
*/
|
typedef struct
|
{
|
uint32_t FTM_ChannelPair; /*!< ͨµÀ¶Ô */
|
uint32_t FTM_CaptureMode; /*!< ²¶»ñģʽ: µ¥´Î²¶»ñºÍÁ¬Ðø */
|
uint32_t FTM_Channel_N_Edge; /*!< ͨµÀN±ßÑؼì²â */
|
uint32_t FTM_Channel_Np1_Edge; /*!< ͨµÀN+1±ßÑؼì²â */
|
|
}FTM_DualEdgeCaptureTypeDef, *FTM_DualEdgeCaptureConfigPtr;
|
|
|
|
/* Exported constants --------------------------------------------------------*/
|
/** @defgroup FTM_Exported_Constants FTMÄ£¿éʹÓòÎÊý¶¨Òå
|
* @{
|
*/
|
|
/** @defgroup FTM_Deinit_Value FTM¼Ä´æÆ÷ĬÈÏÖµ
|
* @{
|
*/
|
#define FTM_MOD_INIT ((uint32_t)20000-(uint32_t)1) /*!< MOD inite value */
|
#define FTM_C0V_INIT (uint32_t)1000 /*!< C0V inite value */
|
#define FTM_C1V_INIT (uint32_t)1000 /*!< C1V inite value */
|
#define FTM_C2V_INIT (uint32_t)1000 /*!< C2V inite value */
|
#define FTM_C3V_INIT (uint32_t)1000 /*!< C3V inite value */
|
#define FTM_C4V_INIT (uint32_t)1000 /*!< C4V inite value */
|
#define FTM_C5V_INIT (uint32_t)1000 /*!< C5V inite value */
|
#define FTM_C6V_INIT (uint32_t)1000 /*!< C6V inite value */
|
#define FTM_C7V_INIT (uint32_t)1000 /*!< C7V inite value */
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_Clocksource_Seclect FTMʱÖÓÔ´Ñ¡Ôñ¶¨Òå
|
* @{
|
*/
|
#define FTM_CLOCK_NOCLOCK 0 /*!< δѡ¶¨Ê±ÖÓ£¬¸ÃÉèÖÃÉúЧºó¿É½ûÓÃFTM¼ÆÊýÆ÷ */
|
#define FTM_CLOCK_SYSTEMCLOCK 1 /*!< System clock */
|
#define FTM_CLOCK_FIXEDFREQCLOCK 2 /*!< Fixed Freq Clock */
|
#define FTM_CLOCK_EXTERNALCLOCK 3 /*!< External Clock */
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_Clockprescale_Seclect FTMʱÖÓ·ÖƵѡÔñ¶¨Òå
|
* @{
|
*/
|
#define FTM_CLOCK_PS_DIV1 0 /*!< 1·ÖƵ */
|
#define FTM_CLOCK_PS_DIV2 1 /*!< 2·ÖƵ */
|
#define FTM_CLOCK_PS_DIV4 2 /*!< 4·ÖƵ */
|
#define FTM_CLOCK_PS_DIV8 3 /*!< 8·ÖƵ */
|
#define FTM_CLOCK_PS_DIV16 4 /*!< 16·ÖƵ */
|
#define FTM_CLOCK_PS_DIV32 5 /*!< 32·ÖƵ */
|
#define FTM_CLOCK_PS_DIV64 6 /*!< 64·ÖƵ */
|
#define FTM_CLOCK_PS_DIV128 7 /*!< 128·ÖƵ */
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_Deadtime_Clockprescale_Seclect FTMËÀÇøʱ¼äʱÖÓ·ÖƵѡÔñ¶¨Òå
|
* @{
|
*/
|
#define FTM_DEADTIME_DTPS_DIV1 0 /*!< 1·ÖƵ */
|
#define FTM_DEADTIME_DTPS_DIV4 2 /*!< 4·ÖƵ */
|
#define FTM_DEADTIME_DTPS_DIV16 3 /*!< 16·ÖƵ */
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_Channels_Modes_Definition FTMͨµÀģʽ¶¨Òå
|
* @{
|
*/
|
#define FTM_PWMMODE_EDGEALLIGNED (uint8_t)1 /*!< ±ßÑضÔÆëPWM */
|
#define FTM_PWMMODE_CENTERALLIGNED (uint8_t)2 /*!< ÖÐÐĶÔÆëPWM */
|
#define FTM_PWMMODE_COMBINE (uint8_t)3 /*!< ×éºÏPWM */
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_PWM_High/Low_TruePulse FTM_PWM¸ß/µÍÕæʵÂö³å
|
|
* @{
|
*/
|
#define FTM_PWM_HIGHTRUEPULSE 2u /*!< ¸ßÕæÂö³å£¨Í¨µÀ(n)Æ¥ÅäʱÖÃλ£¬Í¨µÀ(n+1)Æ¥ÅäʱÇåÁ㣩 */
|
#define FTM_PWM_LOWTRUEPULSE 1u /*!< µÍÕæÂö³å£¨Í¨µÀ(n)Æ¥ÅäʱÇåÁ㣬ͨµÀ(n+1)Æ¥ÅäʱÖÃλ */
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_InputcaptureEdge_Seclect FTMÊäÈ벶»ñ±ßÑØÀàÐÍÑ¡Ôñ
|
* @{
|
*/
|
#define FTM_INPUTCAPTURE_RISINGEDGE 1u /*!< ÉÏÉýÑØ */
|
#define FTM_INPUTCAPTURE_FALLINGEDGE 2u /*!< ϽµÑØ */
|
#define FTM_INPUTCAPTURE_BOTHEDGE 3u /*!< Ë«±ßÑØ */
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_InputcaptureDualEdge_Seclect FTMÊäÈ벶»ñË«±ßÑØÀàÐÍÑ¡Ôñ
|
* @{
|
*/
|
#define FTM_INPUTCAPTURE_DUALEDGE_NOEDGE 0u /*!< ÎÞ±ßÑØ */
|
#define FTM_INPUTCAPTURE_DUALEDGE_RISING 1u /*!< ÉÏÉýÑØ */
|
#define FTM_INPUTCAPTURE_DUALEDGE_FALLING 2u /*!< ϽµÑØ */
|
#define FTM_INPUTCAPTURE_DUALEDGE_BOTHEDGE 3u /*!< Ë«±ßÑØ */
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_DualCapture_Mode FTMË«±È½Ïģʽ
|
* @{
|
*/
|
#define FTM_INPUTCAPTURE_DUALEDGE_ONESHOT 2u /*!< µ¥´Î²¶»ñģʽ */
|
#define FTM_INPUTCAPTURE_DUALEDGE_CONTINUOUS 1u /*!< Á¬Ðø²¶»ñģʽ */
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_OutCompare_Mode FTMÊä³ö±È½Ïģʽ
|
* @{
|
*/
|
#define FTM_OUTPUT_TOGGLE 1u /*!< Æ¥ÅäʱÇл»Êä³ö */
|
#define FTM_OUTPUT_CLEAR 2u /*!< Æ¥ÅäʱÇåÁãÊä³ö */
|
#define FTM_OUTPUT_SET 3u /*!< Æ¥ÅäʱÖÃλÊä³ö */
|
/**
|
* @}
|
*/
|
|
|
/** @defgroup FTM_SYNC_TRIGGER_List FTMͬ²½´¥·¢¹¦ÄÜÁбí
|
* @{
|
*/
|
#define FTM_SYNC_TRIGGER_TRIGGER0 0x10 /*!< ͬ²½Ó²¼þ´¥·¢0 */
|
#define FTM_SYNC_TRIGGER_TRIGGER1 0x20 /*!< ͬ²½Ó²¼þ´¥·¢1 */
|
#define FTM_SYNC_TRIGGER_TRIGGER2 0x40 /*!< ͬ²½Ó²¼þ´¥·¢2 */
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_Update_SYNC_TRIGGER_List FTM¸üÐÂͬ²½´¥·¢¹¦ÄÜÁбí
|
* @{
|
*/
|
#define FTM_UPDATE_RISINGCLK 0u /*!< ¼Ä´æÆ÷½«ÔÚËùÓÐSYSCLKµÄÉÏÉýÑØÒÔÆ仺³åÇøµÄÊýÖµ½øÐиüР*/
|
#define FTM_UPDATE_PWMSYNC 1u /*!< ¼Ä´æÆ÷½öͨ¹ýPWM ͬ²½ÒÔÆ仺³åÇøÖµ½øÐиüР*/
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_Synchronization_Mode_list FTMͬ²½Ä£Ê½
|
* @{
|
*/
|
#define FTM_SYNCMODE_LEGACY 0u /*!< Ñ¡Ôñ´«Í³PWMͬ²½ */
|
#define FTM_SYNCMODE_ENHANCED 1u /*!< Ñ¡ÔñÔöÇ¿PWMͬ²½ */
|
/**
|
* @}
|
*/
|
|
|
/** @defgroup FTM_PWM_Synchronization_Mode_list FTM_PWMÈíÓ²¼þ´¥·¢Ä£Ê½Ñ¡Ôñ
|
* @{
|
*/
|
#define FTM_PWMSYNC_NORESTRICT 0u /*!< ÎÞÏÞÖÆ£¬Ñ¡Ôñ¿ÉÓÃÓÚMOD¡¢CnV¡¢OUTMASK ºÍFTM ¼ÆÊýÆ÷ͬ²½µÄÈí¼þºÍÓ²¼þ´¥·¢ */
|
#define FTM_PWMSYNC_SWANDHW 1u /*!< Èí¼þ´¥·¢Ö»ÄÜÓÃÓÚMOD ºÍCnV ͬ²½£¬Ó²¼þ´¥·¢Ö»ÄÜÓÃÓÚFTM¼ÆÊýÆ÷ͬ²½ */
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_Hardware_Trigger_Mode_list FTMÓ²¼þ´¥·¢Ä£Ê½ÆÁ±Î
|
* @{
|
*/
|
#define FTM_HWTRIGMODE_CLEAR 0u /*!< ¼ì²âµ½Ó²¼þ´¥·¢jʱ£¨j=0¡¢1¡¢2£©£¬FTMÇåÁãTRIGjλ */
|
#define FTM_HWTRIGMODE_UNCLEAR 1u /*!< ¼ì²âµ½Ó²¼þ´¥·¢jʱ£¨j=0¡¢1¡¢2£©£¬FTM²»ÇåÁãTRIGjλ */
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_Synconf_Reg_List FTMͬ²½
|
* @{
|
*/
|
#define FTM_SYNCONF_CNTREG 0u /*!< FTMͬ²½¼ÆÊýÆ÷ */
|
#define FTM_SYNCONF_MODCNTINCVREG 1u /*!< MOD, CNTIN,ºÍCVͬ²½¼Ä´æÆ÷ */
|
#define FTM_SYNCONF_OUTMASKREG 2u /*!< ͬ²½Êä³öÆÁ±Î */
|
#define FTM_SYNCONF_INVCTRLREG 3u /*!< INVCTRL¼Ä´æÆ÷ͬ²½ */
|
#define FTM_SYNCONF_SWOCTRLREG 4u /*!< SWOCTRL¼Ä´æÆ÷ͬ²½ */
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_Synchronization_Mode_Seclect FTMͬ²½Ä£Ê½´¥·¢Ñ¡Ôñ
|
* @{
|
*/
|
#define FTM_SYNCONF_SWTRIGGER 0u /*!< ͬ²½Èí¼þ´¥·¢ */
|
#define FTM_SYNCONF_HWTRIGGER 1u /*!< ͬ²½Ó²¼þ´¥·¢ */
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_Reinitialization_List FTM¸üÐÂÊä³öÖµ
|
* @{
|
*/
|
#define FTM_REINIT_NORMALLY 0u /*!< FTM¼ÆÊýÆ÷¼ÌÐøÕý³£¼ÆÊý */
|
#define FTM_REINIT_UPDATED 1u /*!< FTM¼ÆÊýÆ÷ÒÔÆä³õʼֵ¸üР*/
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_Channel_List FTMͨµÀÁбí
|
* @{
|
*/
|
#define FTM_CHANNEL0 0u /*!< FTMxͨµÀ0 */
|
#define FTM_CHANNEL1 1u /*!< FTMxͨµÀ1 */
|
#define FTM_CHANNEL2 2u /*!< FTMxͨµÀ2 */
|
#define FTM_CHANNEL3 3u /*!< FTMxͨµÀ3 */
|
#define FTM_CHANNEL4 4u /*!< FTMxͨµÀ4 */
|
#define FTM_CHANNEL5 5u /*!< FTMxͨµÀ5 */
|
#define FTM_CHANNEL6 6u /*!< FTMxͨµÀ6 */
|
#define FTM_CHANNEL7 7u /*!< FTMxͨµÀ7 */
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_ChannelPair_List FTM×éºÏģʽͨµÀÁбí
|
* @{
|
*/
|
#define FTM_CHANNELPAIR0 0u /*!< ͨµÀ¶Ô0:ch0 & ch1 */
|
#define FTM_CHANNELPAIR1 2u /*!< ͨµÀ¶Ô1:ch2 & ch3 */
|
#define FTM_CHANNELPAIR2 4u /*!< ͨµÀ¶Ô2:ch4 & ch5 */
|
#define FTM_CHANNELPAIR3 6u /*!< ͨµÀ¶Ô3:ch6 & ch7 */
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_ChannelFlag_List FTMͨµÀ±êÖ¾Áбí
|
* @{
|
*/
|
#define FTM_CHANNEL0_FLAG 0u /*!< FTMͨµÀ±êÖ¾0 */
|
#define FTM_CHANNEL1_FLAG 1u /*!< FTMͨµÀ±êÖ¾1 */
|
#define FTM_CHANNEL2_FLAG 2u /*!< FTMͨµÀ±êÖ¾2 */
|
#define FTM_CHANNEL3_FLAG 3u /*!< FTMͨµÀ±êÖ¾3 */
|
#define FTM_CHANNEL4_FLAG 4u /*!< FTMͨµÀ±êÖ¾4 */
|
#define FTM_CHANNEL5_FLAG 5u /*!< FTMͨµÀ±êÖ¾5 */
|
#define FTM_CHANNEL6_FLAG 6u /*!< FTMͨµÀ±êÖ¾6 */
|
#define FTM_CHANNEL7_FLAG 7u /*!< FTMͨµÀ±êÖ¾7 */
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_IntialValue_list FTM³õʼֵÁбí
|
* @{
|
*/
|
#define FTM_INITIALVALUE0 0u /*!< FTM³õʼֵ0 */
|
#define FTM_INITIALVALUE1 1u /*!< FTM³õʼֵ1 */
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_ChannelPolarity_List FTMͨµÀ¼«ÐÔÁбí
|
* @{
|
*/
|
#define FTM_CHANNELPOLARITY_HIGH 0u /*!< FTMͨµÀ¼«ÐÔΪ¸ßµçƽ */
|
#define FTM_CHANNELPOLARITY_LOW 1u /*!< FTMͨµÀ¼«ÐÔΪµÍµçƽ */
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_FaultDetectionFlag_List FTMͨµÀ´íÎó±êÖ¾Áбí
|
* @{
|
*/
|
#define FTM_FAULTDETECTION_FLAG0 0u /*!< ¹ÊÕϼì²â±êÖ¾0 */
|
#define FTM_FAULTDETECTION_FLAG1 1u /*!< ¹ÊÕϼì²â±êÖ¾1 */
|
#define FTM_FAULTDETECTION_FLAG2 2u /*!< ¹ÊÕϼì²â±êÖ¾2 */
|
#define FTM_FAULTDETECTION_FLAG3 3u /*!< ¹ÊÕϼì²â±êÖ¾3 */
|
/**
|
* @}
|
*/
|
|
|
/** @defgroup FaultControlChanne_List FTM¹ÊÕÏ¿ØÖÆͨµÀÁбí
|
* @{
|
*/
|
#define FaultControlChanne0 0x00000040u /*!< ¹ÊÕÏ¿ØÖÆͨµÀ0 */
|
#define FaultControlChanne1 0x00004000u /*!< ¹ÊÕÏ¿ØÖÆͨµÀ1 */
|
#define FaultControlChanne2 0x00400000u /*!< ¹ÊÕÏ¿ØÖÆͨµÀ2 */
|
#define FaultControlChanne3 0x40000000u /*!< ¹ÊÕÏ¿ØÖÆͨµÀ3 */
|
/**
|
* @}
|
*/
|
|
|
|
|
/** @defgroup FTM_InputFilterChannel_List FTMÊäÈëÂ˲¨Í¨µÀÁбí
|
* @{
|
*/
|
#define FTM_INPUTFILTER_CHANNEL0 0u /*!< ͨµÀ0ÊäÈëÂ˲¨ */
|
#define FTM_INPUTFILTER_CHANNEL1 1u /*!< ͨµÀ1ÊäÈëÂ˲¨ */
|
#define FTM_INPUTFILTER_CHANNEL2 2u /*!< ͨµÀ2ÊäÈëÂ˲¨ */
|
#define FTM_INPUTFILTER_CHANNEL3 3u /*!< ͨµÀ3ÊäÈëÂ˲¨ */
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_FaultInput_List FTM¹ÊÕÏÊäÈëÁбí
|
* @{
|
*/
|
#define FTM_FAULT_INPUT0 0u /*!< ¹ÊÕÏÊäÈë0 */
|
#define FTM_FAULT_INPUT1 1u /*!< ¹ÊÕÏÊäÈë1 */
|
#define FTM_FAULT_INPUT2 2u /*!< ¹ÊÕÏÊäÈë2 */
|
#define FTM_FAULT_INPUT3 3u /*!< ¹ÊÕÏÊäÈë3 */
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_FaultInputFilter_List FTM¹ÊÕÏÂ˲¨ÊäÈëÁбí
|
* @{
|
*/
|
#define FTM_FAULTINPUT_FILTER0 0u /*!< ¹ÊÕÏÂ˲¨ÊäÈë0 */
|
#define FTM_FAULTINPUT_FILTER1 1u /*!< ¹ÊÕÏÂ˲¨ÊäÈë1 */
|
#define FTM_FAULTINPUT_FILTER2 2u /*!< ¹ÊÕÏÂ˲¨ÊäÈë2 */
|
#define FTM_FAULTINPUT_FILTER3 3u /*!< ¹ÊÕÏÂ˲¨ÊäÈë3 */
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_FaultPolarityFilter_List FTM¹ÊÕÏÂ˲¨ÊäÈëÁбí
|
* @{
|
*/
|
#define FTM_FAULTINPOLARITY_HIGH 0u /*!< ¹ÊÕÏÊäÈ뼫ÐÔΪ¸ß */
|
#define FTM_FAULTINPOLARITY_LOW 1u /*!< ¹ÊÕÏÊäÈ뼫ÐÔΪµÍ */
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_invert_pair_channel_list FTMͨµÀ·´×ª
|
* @{
|
*/
|
#define FTM_INVERT_PAIRCHANNEL0 0u /*!< ͨµÀ¶Ô0·´×ªÊ¹ÄÜ */
|
#define FTM_INVERT_PAIRCHANNEL1 1u /*!< ͨµÀ¶Ô1·´×ªÊ¹ÄÜ */
|
#define FTM_INVERT_PAIRCHANNEL2 2u /*!< ͨµÀ¶Ô2·´×ªÊ¹ÄÜ */
|
#define FTM_INVERT_PAIRCHANNEL3 3u /*!< ͨµÀ¶Ô3·´×ªÊ¹ÄÜ */
|
/**
|
* @}
|
*/
|
|
/** @defgroup FTM_Software_Control_Outvalue_list FTMÈí¼þ¿ØÖÆÊä³öÖµÁбí
|
* @{
|
*/
|
#define FTM_SWCONTROL_OUT0 0u /*!< FTMÈí¼þ¿ØÖÆÊä³öֵǿÖÆΪ0 */
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#define FTM_SWCONTROL_OUT1 1u /*!< FTMÈí¼þ¿ØÖÆÊä³öֵǿÖÆΪ1 */
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/**
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* @}
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*/
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/** @defgroup FTM_ChannelMatch_list FTMͨµÀÆ¥Åä¿ØÖÆÁбí
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* @{
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*/
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#define FTM_CHANNELMATCH_NOTINCLUDE 0u /*!< Æ¥Åä¹ý³ÌÖв»°üÀ¨Í¨µÀ */
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#define FTM_CHANNELMATCH_INCLUDE 1u /*!< Æ¥Åä¹ý³ÌÖаüÀ¨Í¨µÀ */
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/**
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* @}
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*/
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/** @defgroup FTM_Software_Sync_Activate FTMÈí¼þͬ²½´¥·¢¹¦ÄÜ
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* @{
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*/
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#define FTM_SOFTWARE_SYN_CNT FTM_SYNCONF_SWRSTCNT_MASK
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#define FTM_SOFTWARE_SYN_MOD_CNTIN_CV FTM_SYNCONF_SWWRBUF_MASK
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#define FTM_SOFTWARE_SYN_OUTMASK FTM_SYNCONF_SWOM_MASK
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#define FTM_SOFTWARE_SYN_INVCTRL FTM_SYNCONF_SWINVC_MASK
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#define FTM_SOFTWARE_SYN_OUTCTRL FTM_SYNCONF_SWSOC_MASK
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/**
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* @}
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*/
|
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/** @defgroup FTM_Shardware_Sync_Activate FTMÓ²¼þͬ²½´¥·¢¹¦ÄÜ
|
* @{
|
*/
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#define FTM_HARDWARE_SYN_CNT FTM_SYNCONF_HWRSTCNT_MASK
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#define FTM_HARDWARE_SYN_MOD_CNTIN_CV FTM_SYNCONF_HWWRBUF_MASK
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#define FTM_HARDWARE_SYN_OUTMASK FTM_SYNCONF_HWOM_MASK
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#define FTM_HARDWARE_SYN_INVCTRL FTM_SYNCONF_HWINVC_MASK
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#define FTM_HARDWARE_SYN_OUTCTRL FTM_SYNCONF_HWSOC_MASK
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/**
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* @}
|
*/
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|
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/** @defgroup FTM Interrupt Enable FTMÖжÏʹÄÜ
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* @{
|
*/
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typedef enum {
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FTM_ALLDISABLE= 0, /*!< ËùÓÐͨµÀ½ûÓùÊÕÏ¿ØÖÆ */
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FTM_EVENENABLE_MANUALCLEAR, /*!< ½öÕë¶ÔżÊýÐŵÀ£¨ÐŵÀ0¡¢2¡¢4 ºÍ6£©Ê¹ÄܹÊÕÏ¿ØÖÆ£¬ËùѡģʽΪÊÖ¶¯¹ÊÕÏÇåÁã */
|
FTM_ALLENABLE_MANUALCLEAR, /*!< ËùÓÐͨµÀʹÄܹÊÕÏ¿ØÖÆ£¬ËùѡģʽΪÊÖ¶¯¹ÊÕÏÇåÁã */
|
FTM_ALLENABLE_AUTOCLEAR /*!< ËùÓÐͨµÀʹÄܹÊÕÏ¿ØÖÆ£¬ËùѡģʽΪ×Ô¶¯¹ÊÕÏÇåÁã */
|
|
} FTM_FaultControlModeDef;
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/**
|
* @}
|
*/
|
|
/**
|
* @}
|
*/
|
|
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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void FTM_WriteProtectEnable(FTM_Type* FTMx);
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void FTM_WriteProtectDisable(FTM_Type* FTMx);
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void FTM_DeInit(FTM_Type* FTMx);
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void FTM_Init(FTM_Type* FTMx, const FTM_InitTypeDef* FTM_InitStruct);
|
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void FTM_EdgeAlignedPWMInit(FTM_Type* FTMx, uint8_t FTM_Channel, uint8_t PWMEdgeSelect);
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void FTM_CenterAlignedPWMInit(FTM_Type* FTMx, uint8_t FTM_Channel, uint8_t PWMEdgeSelect);
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void FTM_CombinePWMPWMInit(FTM_Type* FTMx, const FTM_CombinePWMTypeDef *FTM_CombinePWMStruct);
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void FTM_PWMInit(FTM_Type* FTMx, uint8_t PWMModeSelect, uint8_t PWMEdgeSelect);
|
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void FTM_InputCaptureInit(FTM_Type* FTMx, uint8_t FTM_Channel, uint8_t CaptureMode);
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void FTM_DualEdgeCaptureInit(FTM_Type* FTMx, const FTM_DualEdgeCaptureTypeDef* FTM_DualEdgeStruct);
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void FTM_OutputCompareInit(FTM_Type* FTMx, uint8_t FTM_Channel, uint32_t CompareMode);
|
|
void FTM_OverflowITCmd(FTM_Type* FTMx, FunctionalState NewState);
|
FlagStatus FTM_GetOverFlowFlag(const FTM_Type* FTMx);
|
void FTM_ClrOverFlowFlag(FTM_Type* FTMx);
|
|
uint16_t FTM_GetCountValue(const FTM_Type* FTMx);
|
void FTM_SetModValue(FTM_Type* FTMx, uint16_t ModValue);
|
void FTM_SetCountInitValue(FTM_Type* FTMx, uint16_t InitialValue);
|
|
void FTM_ChannelIntCmd(FTM_Type* FTMx, uint8_t FTM_Channel, FunctionalState NewState);
|
FlagStatus FTM_GetChannelFlag(const FTM_Type* FTMx, uint8_t FTM_Channel);
|
void FTM_ClrChannelFlag(FTM_Type* FTMx, uint8_t FTM_Channel);
|
void FTM_SetChannelValue(FTM_Type* FTMx, uint8_t FTM_Channel, uint16_t ChannelValue);
|
uint16_t FTM_GetChannelValue(const FTM_Type* FTMx, uint8_t FTM_Channel );
|
|
uint32_t FTM_GetStatusRegFlag(const FTM_Type* FTMx);
|
void FTM_ClrStatusRegFlag(FTM_Type* FTMx);
|
FlagStatus FTM_GetStatusChannelFlag(const FTM_Type* FTMx, uint8_t ChannelFlag);
|
void FTM_ClrStatusChannelFlag(FTM_Type* FTMx, uint8_t ChannelFlag);
|
|
void FTM_FaultITCmd(FTM_Type* FTMx, FunctionalState NewState);
|
void FTM_SetFaultControlMode(FTM_Type* FTMx, FTM_FaultControlModeDef FTM_FaultControlMode);
|
void FTM_CaptureTestCmd(FTM_Type* FTMx, FunctionalState NewState);
|
|
void FTM_SoftwareSync(FTM_Type* FTMx, FunctionalState NewState);
|
void FTM_HardwareSync(FTM_Type* FTMx, uint8_t TriggerN, FunctionalState NewState);
|
void FTM_RegSyncCmd(FTM_Type* FTMx, uint8_t TriggerType, uint8_t RegType, FunctionalState NewState);
|
void FTM_OutMaskSync(FTM_Type* FTMx, uint8_t update);
|
void FTM_CNTINCSync(FTM_Type* FTMx, uint8_t update);
|
void FTM_INVCSync(FTM_Type* FTMx, uint8_t update);
|
void FTM_SWOCSync(FTM_Type* FTMx, uint8_t update);
|
void FTM_SetSyncMode(FTM_Type* FTMx, uint8_t mode);
|
void FTM_SetPWMSyncMode(FTM_Type* FTMx, uint8_t mode);
|
void FTM_SetHardwareTriggerMode(FTM_Type* FTMx, uint8_t mode);
|
|
void FTM_CNTMAXCmd(FTM_Type* FTMx, FunctionalState NewState);
|
void FTM_CNTMINCmd(FTM_Type* FTMx, FunctionalState NewState);
|
void FTM_Reinitialization(FTM_Type* FTMx, uint8_t mode);
|
|
void FTM_SetInitOut(FTM_Type* FTMx, uint8_t initialvalue);
|
void FTM_SetChannelOutInitValue(FTM_Type* FTMx,uint8_t FTM_Channel, uint8_t initialvalue);
|
|
void FTM_SetOutMask(FTM_Type* FTMx, uint8_t outmask);
|
void FTM_SetChannelOutMaskCmd(FTM_Type* FTMx, uint8_t FTM_Channel, FunctionalState NewState);
|
|
void FTM_PWMDeadtimeSet(FTM_Type* FTMx, uint32_t PrescalerValue, uint32_t DeadtimeValue);
|
|
FlagStatus FTM_GetExternalTriggerFlag(const FTM_Type* FTMx);
|
void FTM_ClrExternalTriggerFlag(FTM_Type* FTMx);
|
void FTM_SetChnTriggerCmd(FTM_Type* FTMx, uint8_t FTM_Channel, FunctionalState NewState);
|
void FTM_SetInitTriggerCmd(FTM_Type* FTMx, FunctionalState NewState);
|
|
void FTM_SetChannelsPolarity(FTM_Type* FTMx, uint8_t PolarityValue);
|
void FTM_SetSingleChannelPolarity(FTM_Type* FTMx, uint8_t FTM_Channel, uint8_t FTM_Polarity);
|
|
FlagStatus FTM_GetFaultDetectLogicORFlag(const FTM_Type* FTMx);
|
FlagStatus FTM_GetFaultDetectFlag(const FTM_Type* FTMx, uint8_t FaultDetectFlag);
|
uint32_t FTM_GetFaultInLogicORValue(const FTM_Type* FTMx);
|
void FTM_ClrFaultDetectLogicORFlag(FTM_Type* FTMx);
|
void FTM_ClrFaultDetectFlag(FTM_Type* FTMx, uint8_t FaultDetectFlag);
|
|
void FTM_SetChannelInFilter(FTM_Type* FTMx, uint8_t FTM_FilterChannel, uint32_t FilterValue);
|
void FTM_SetInCapFilter(FTM_Type* FTMx, uint16_t filter);
|
|
void FTM_FaultPinCmd(FTM_Type* FTMx, uint8_t FaultInput, FunctionalState NewState);
|
void FTM_FaultPinFilterCmd(FTM_Type* FTMx, uint8_t FaultFilter, FunctionalState NewState);
|
void FTM_SetFaultInFilter(FTM_Type* FTMx, uint32_t FilterValue);
|
|
void FTM_GTBEENCmd(FTM_Type* FTMx, FunctionalState NewState);
|
void FTM_GTBEOUTCmd(FTM_Type* FTMx, FunctionalState NewState);
|
void FTM_SetDebugModeBehavior(FTM_Type* FTMx, uint32_t DebugMode);
|
|
void FTM_SetFaultInPolarity(FTM_Type* FTMx, uint8_t FaultInput, uint8_t polarity);
|
|
void FTM_PairChannelsInvertCmd(FTM_Type* FTMx, uint8_t channelpair, FunctionalState NewState);
|
|
void FTM_SWOutControlCmd(FTM_Type* FTMx, uint8_t FTM_Channel, FunctionalState NewState);
|
void FTM_SetSWOutControlValue(FTM_Type* FTMx, uint8_t FTM_Channel, uint8_t outvalue);
|
|
void FTM_SetLoadMatchChannels(FTM_Type* FTMx, uint32_t Matchchannel);
|
void FTM_SetLoadMatchChannel(FTM_Type* FTMx, uint8_t FTM_Channel, uint8_t include);
|
void FTM_SetLoadCmd(FTM_Type* FTMx, FunctionalState NewState);
|
|
|
void FTM_CVSyncEnable(FTM_Type* FTMx,uint8_t FTM_Channel,FunctionalState State);
|
|
void FTM_SoftSyncActivateTypeEnable(FTM_Type* FTMx, uint32_t type, FunctionalState NewState);
|
void FTM_HardSyncActivateTypeEnable(FTM_Type* FTMx, uint32_t type, FunctionalState NewState);
|
|
void FTM_SyncLoadEnable(FTM_Type* FTMx, FunctionalState NewState);
|
void FTM_FaultControlEnable(FTM_Type* FTMx, uint32_t FaultControlChannel,FunctionalState NewState);
|
#ifdef __cplusplus
|
}
|
#endif
|
|
#endif /*__XL_FTM_H__ */
|
/**
|
* @}
|
*/
|
|
/**
|
* @}
|
*/
|
