/*!
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\file gd32e23x_pmu.h
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\brief definitions for the PMU
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\version 2019-02-19, V1.0.0, firmware for GD32E23x
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*/
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/*
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Copyright (c) 2019, GigaDevice Semiconductor Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32E23X_PMU_H
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#define GD32E23X_PMU_H
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#include "gd32e23x.h"
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/* PMU definitions */
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#define PMU PMU_BASE /*!< PMU base address */
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/* registers definitions */
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#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */
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#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */
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/* bits definitions */
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/* PMU_CTL */
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#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */
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#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */
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#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */
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#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */
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#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */
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#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */
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#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */
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#define PMU_CTL_LDOVS_0 BIT(14) /*!< LDO output voltage select */
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#define PMU_CTL_LDOVS_1 BIT(15) /*!< LDO output voltage select */
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#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */
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/* PMU_CS */
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#define PMU_CS_WUF BIT(0) /*!< wakeup flag */
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#define PMU_CS_STBF BIT(1) /*!< standby flag */
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#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */
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#define PMU_CS_WUPEN0 BIT(8) /*!< wakeup pin enable */
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#ifdef GD32E230
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#define PMU_CS_WUPEN1 BIT(9) /*!< wakeup pin enable */
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#endif /* GD32E230 */
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#define PMU_CS_WUPEN5 BIT(13) /*!< wakeup pin enable */
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#define PMU_CS_WUPEN6 BIT(14) /*!< wakeup pin enable */
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/* constants definitions */
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/* PMU low voltage detector threshold definitions */
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#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5))
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#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */
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#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */
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#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */
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#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */
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#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */
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#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */
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#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */
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#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */
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/* PMU LDO output voltage select definitions */
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#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14))
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#define PMU_LDOVS_HIGH CTL_LDOVS(1) /*!< LDO output voltage high mode */
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#define PMU_LDOVS_LOW CTL_LDOVS(2) /*!< LDO output voltage low mode */
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/* PMU ldo definitions */
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#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO operates normally when PMU enter deepsleep mode */
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#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */
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/* PMU flag definitions */
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#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */
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#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */
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#define PMU_FLAG_LVD PMU_CS_LVDF /*!< LVD flag status */
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/* PMU WKUP pin definitions */
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#define PMU_WAKEUP_PIN0 PMU_CS_WUPEN0 /*!< WKUP Pin 0 (PA0) enable */
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#ifdef GD32E230
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#define PMU_WAKEUP_PIN1 PMU_CS_WUPEN1 /*!< WKUP Pin 1 (PC13) enable */
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#endif /* GD32E230 */
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#define PMU_WAKEUP_PIN5 PMU_CS_WUPEN5 /*!< WKUP Pin 5 (PB5) enable */
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#define PMU_WAKEUP_PIN6 PMU_CS_WUPEN6 /*!< WKUP Pin 6 (PB15) enable */
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/* PMU flag reset definitions */
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#define PMU_FLAG_RESET_WAKEUP PMU_CTL_WURST /*!< wakeup flag reset */
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#define PMU_FLAG_RESET_STANDBY PMU_CTL_STBRST /*!< standby flag reset */
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/* PMU command constants definitions */
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#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */
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#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */
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/* function declarations */
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/* reset PMU registers */
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void pmu_deinit(void);
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/* select low voltage detector threshold */
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void pmu_lvd_select(uint32_t lvdt_n);
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/* select LDO output voltage */
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void pmu_ldo_output_select(uint32_t ldo_output);
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/* disable PMU lvd */
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void pmu_lvd_disable(void);
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/* set PMU mode */
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/* PMU work in sleep mode */
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void pmu_to_sleepmode(uint8_t sleepmodecmd);
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/* PMU work in deepsleep mode */
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void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd);
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/* PMU work in standby mode */
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void pmu_to_standbymode(uint8_t standbymodecmd);
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/* enable PMU wakeup pin */
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void pmu_wakeup_pin_enable(uint32_t wakeup_pin);
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/* disable PMU wakeup pin */
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void pmu_wakeup_pin_disable(uint32_t wakeup_pin);
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/* backup related functions */
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/* enable backup domain write */
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void pmu_backup_write_enable(void);
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/* disable backup domain write */
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void pmu_backup_write_disable(void);
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/* flag functions */
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/* clear flag bit */
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void pmu_flag_clear(uint32_t flag_clear);
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/* get flag state */
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FlagStatus pmu_flag_get(uint32_t flag);
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#endif /* GD32E23X_PMU_H */
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