| | |
| | | #include "SEGGER_RTT_Conf.h" |
| | | #include "SEGGER_RTT.h" |
| | | static volatile motor_rotate_t motor_drive = {0}; |
| | | static uint32_t motor_pluse = 0; |
| | | static uint32_t motor_pluse = 1500; |
| | | static volatile uint8_t motor_step = 0; |
| | | static void motor_phasechange(void); |
| | | static void update_speed_dir(uint8_t dir_in); |
| | | |
| | |
| | | /* ¶ÁÈ¡»ô¶û´«¸ÐÆ÷ U µÄ״̬ */ |
| | | if (Get_HallSensorA_State()) |
| | | { |
| | | state |= 0x01U << 0; |
| | | state |= (0x01U << 0); |
| | | } |
| | | |
| | | /* ¶ÁÈ¡»ô¶û´«¸ÐÆ÷ V µÄ״̬ */ |
| | | if (Get_HallSensorB_State()) |
| | | { |
| | | state |= 0x01U << 1; |
| | | state |= (0x01U << 1); |
| | | } |
| | | |
| | | /* ¶ÁÈ¡»ô¶û´«¸ÐÆ÷ W µÄ״̬ */ |
| | | if (Get_HallSensorC_State()) |
| | | { |
| | | state |= 0x01U << 2; |
| | | state |= (0x01U << 2); |
| | | } |
| | | |
| | | return state; // ·µ»Ø´«¸ÐÆ÷״̬ |
| | |
| | | void HAL_HallExti_TriggerCallback(void) |
| | | { |
| | | uint8_t step = 0; |
| | | step = get_hall_state(); |
| | | /* »ñÈ¡»ô¶û´«¸ÐÆ÷Òý½Å״̬,×÷Ϊ»»ÏàµÄÒÀ¾Ý */ |
| | | motor_step = get_hall_state(); |
| | | // /* »ñÈ¡»ô¶û´«¸ÐÆ÷Òý½Å״̬,×÷Ϊ»»ÏàµÄÒÀ¾Ý */ |
| | | if (exti_interrupt_flag_get(HALL_A_EXTI | HALL_B_EXTI | HALL_C_EXTI)) // ÅжÏÊÇ·ñÓÉ´¥·¢ÖжϲúÉú |
| | | { |
| | | // update_motor_speed(step, __HAL_TIM_GET_COMPARE(htim, TIM_CHANNEL_1));//TODO Ö÷¶¨Ê±Æ÷´¦»ñµÃ¼ÆÊýʱ¼ä |
| | | update_motor_speed(step, 300u * GetSpeedTimerOutcnt() + timer_counter_read(TIMER2)); |
| | | SEGGER_RTT_printf(0, "Speed is:%d!\n", motor_drive.speed); |
| | | // update_motor_speed(step, __HAL_TIM_GET_COMPARE(htim, TIM_CHANNEL_1)); //TODO Ö÷¶¨Ê±Æ÷´¦»ñµÃ¼ÆÊýʱ¼ä |
| | | update_motor_speed(motor_step, 300u * GetSpeedTimerOutcnt() + timer_counter_read(TIMER2)); |
| | | SEGGER_RTT_printf(0, "Hall state is:%d!\n", motor_step); |
| | | motor_drive.timeout = 0; |
| | | exti_interrupt_flag_clear(HALL_A_EXTI | HALL_B_EXTI | HALL_C_EXTI); |
| | | // // exti_interrupt_flag_clear(HALL_A_EXTI | HALL_B_EXTI | HALL_C_EXTI); |
| | | } |
| | | |
| | | // if (RESET != exti_interrupt_flag_get(EXTI_4)) |
| | | // { |
| | | // SEGGER_RTT_printf(0, "HALL_A_EXTI triggle!\n"); |
| | |
| | | } |
| | | switch (step) |
| | | { |
| | | /* next step: step 2 configuration .A-C` breakover---------------------------- */ |
| | | /* next step: step 3 configuration .W-U` breakover---------------------------- */ |
| | | case 1: |
| | | /* channel U configuration */ |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_U, TIMER_OC_MODE_PWM1); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCX_ENABLE); |
| | | MOTOR_U_L_DISABLE; |
| | | |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCX_DISABLE); |
| | | MOTOR_U_L_ENABLE; |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCXN_DISABLE); |
| | | |
| | | /* channel V configuration */ |
| | |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCXN_DISABLE); |
| | | |
| | | /* channel W configuration */ |
| | | // timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_W, TIMER_OC_MODE_PWM1); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCX_DISABLE); |
| | | MOTOR_W_L_ENABLE; |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_W, TIMER_OC_MODE_PWM0); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCX_ENABLE); |
| | | MOTOR_W_L_DISABLE; |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCXN_ENABLE); |
| | | |
| | | step++; |
| | | break; |
| | | |
| | | /* next step: step 3 configuration .B-C` breakover---------------------------- */ |
| | | /* next step: step 6 configuration .u-v` breakover---------------------------- */ |
| | | case 2: |
| | | /* channel U configuration */ |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCX_DISABLE); |
| | | timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCXN_DISABLE); |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_U, TIMER_OC_MODE_PWM0); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCX_ENABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCXN_DISABLE); |
| | | MOTOR_U_L_DISABLE; |
| | | |
| | | /* channel V configuration */ |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_V, TIMER_OC_MODE_PWM1); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCX_ENABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCXN_DISABLE); |
| | | MOTOR_V_L_DISABLE; |
| | | |
| | | /* channel W configuration */ |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_W, TIMER_OC_MODE_PWM1); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCX_DISABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCXN_ENABLE); |
| | | MOTOR_W_L_ENABLE; |
| | | |
| | | step++; |
| | | break; |
| | | |
| | | /* next step: step 4 configuration .B-A` breakover---------------------------- */ |
| | | case 3: |
| | | /* channel U configuration */ |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_U, TIMER_OC_MODE_PWM1); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCX_DISABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCXN_ENABLE); |
| | | MOTOR_U_L_ENABLE; |
| | | |
| | | /* channel V configuration */ |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_V, TIMER_OC_MODE_PWM1); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCX_ENABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCXN_DISABLE); |
| | | MOTOR_V_L_DISABLE; |
| | | |
| | | /* channel W configuration */ |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCX_DISABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCXN_DISABLE); |
| | | MOTOR_W_L_DISABLE; |
| | | |
| | | step++; |
| | | break; |
| | | |
| | | /* next step: step 5 configuration .C-A` breakover---------------------------- */ |
| | | case 4: |
| | | /* channel U configuration */ |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_U, TIMER_OC_MODE_PWM1); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCX_DISABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCXN_ENABLE); |
| | | MOTOR_U_L_ENABLE; |
| | | |
| | | /* channel V configuration */ |
| | | // timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_V, TIMER_OC_MODE_PWM0); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCX_DISABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCXN_DISABLE); |
| | | MOTOR_V_L_DISABLE; |
| | | MOTOR_V_L_ENABLE; |
| | | |
| | | /* channel W configuration */ |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_W, TIMER_OC_MODE_PWM1); |
| | | // timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_W, TIMER_OC_MODE_PWM0); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCX_DISABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCXN_ENABLE); |
| | | MOTOR_W_L_DISABLE; |
| | | |
| | | break; |
| | | |
| | | /* next step: step 2 configuration .W-V` breakover---------------------------- */ |
| | | case 3: |
| | | /* channel U configuration */ |
| | | // timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_U, TIMER_OC_MODE_PWM0); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCX_DISABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCXN_ENABLE); |
| | | MOTOR_U_L_DISABLE; |
| | | |
| | | /* channel V configuration */ |
| | | // timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_V, TIMER_OC_MODE_PWM0); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCX_DISABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCXN_DISABLE); |
| | | MOTOR_V_L_ENABLE; |
| | | |
| | | /* channel W configuration */ |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_W, TIMER_OC_MODE_PWM0); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCX_ENABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCXN_DISABLE); |
| | | MOTOR_W_L_DISABLE; |
| | | |
| | | step++; |
| | | break; |
| | | |
| | | /* next step: step 6 configuration .C-B` breakover---------------------------- */ |
| | | /* next step: step 5 configuration .V-W` breakover---------------------------- */ |
| | | case 4: |
| | | /* channel U configuration */ |
| | | // timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_U, TIMER_OC_MODE_PWM0); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCX_DISABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCXN_ENABLE); |
| | | MOTOR_U_L_DISABLE; |
| | | |
| | | /* channel V configuration */ |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_V, TIMER_OC_MODE_PWM0); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCXN_ENABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCXN_DISABLE); |
| | | MOTOR_V_L_DISABLE; |
| | | |
| | | /* channel W configuration */ |
| | | // timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_W, TIMER_OC_MODE_PWM0); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCXN_DISABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCXN_DISABLE); |
| | | MOTOR_W_L_ENABLE; |
| | | |
| | | break; |
| | | |
| | | /* next step: step 1 configuration .V-U` breakover---------------------------- */ |
| | | case 5: |
| | | /* channel U configuration */ |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCX_DISABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCXN_DISABLE); |
| | | MOTOR_U_L_DISABLE; |
| | | MOTOR_U_L_ENABLE; |
| | | |
| | | /* channel V configuration */ |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_V, TIMER_OC_MODE_PWM1); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCX_DISABLE); |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_V, TIMER_OC_MODE_PWM0); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCXN_ENABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCXN_ENABLE); |
| | | MOTOR_V_L_ENABLE; |
| | | MOTOR_V_L_DISABLE; |
| | | |
| | | /* channel W configuration */ |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_W, TIMER_OC_MODE_PWM1); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCX_ENABLE); |
| | | // timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_W, TIMER_OC_MODE_PWM0); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCXN_DISABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCXN_DISABLE); |
| | | MOTOR_W_L_DISABLE; |
| | | step++; |
| | | break; |
| | | |
| | | /* next step: step 1 configuration .A-B` breakover---------------------------- */ |
| | | /* next step: step 4 configuration .U-W` breakover---------------------------- */ |
| | | case 6: |
| | | /* channel U configuration */ |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_U, TIMER_OC_MODE_PWM1); |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_U, TIMER_OC_MODE_PWM0); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCX_ENABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCXN_DISABLE); |
| | | MOTOR_U_L_DISABLE; |
| | | |
| | | /* channel V configuration */ |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_V, TIMER_OC_MODE_PWM1); |
| | | // timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_V, TIMER_OC_MODE_PWM0); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCX_DISABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCXN_ENABLE); |
| | | MOTOR_V_L_ENABLE; |
| | | MOTOR_V_L_DISABLE; |
| | | |
| | | /* channel W configuration */ |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCX_DISABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCXN_DISABLE); |
| | | MOTOR_W_L_DISABLE; |
| | | MOTOR_W_L_ENABLE; |
| | | |
| | | step = 1; |
| | | break; |
| | | } |
| | | } |
| | |
| | | extern void stop_pwm_output(void) |
| | | { |
| | | timer_channel_output_state_config(TIMER0, TIMER_CH_0, TIMER_CCX_DISABLE); |
| | | timer_channel_complementary_output_state_config(TIMER0, TIMER_CH_0, TIMER_CCXN_DISABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, TIMER_CH_0, TIMER_CCXN_DISABLE); |
| | | timer_channel_output_state_config(TIMER0, TIMER_CH_1, TIMER_CCX_DISABLE); |
| | | timer_channel_complementary_output_state_config(TIMER0, TIMER_CH_1, TIMER_CCXN_DISABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, TIMER_CH_1, TIMER_CCXN_DISABLE); |
| | | timer_channel_output_state_config(TIMER0, TIMER_CH_2, TIMER_CCX_DISABLE); |
| | | timer_channel_complementary_output_state_config(TIMER0, TIMER_CH_2, TIMER_CCXN_DISABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, TIMER_CH_2, TIMER_CCXN_DISABLE); |
| | | MOTOR_W_L_DISABLE; |
| | | MOTOR_V_L_DISABLE; |
| | | MOTOR_U_L_DISABLE; |
| | | } |
| | | |
| | | /** |
| | |
| | | { |
| | | /* ÉèÖö¨Ê±Æ÷ͨµÀÊä³ö PWM µÄÕ¼¿Õ±È */ |
| | | motor_pluse = pulse; |
| | | //SetPwmDuty(); |
| | | SetPwmDuty(TIMER_CH_0, motor_pluse); |
| | | SetPwmDuty(TIMER_CH_1, motor_pluse); |
| | | SetPwmDuty(TIMER_CH_2, motor_pluse); |
| | | |
| | | if (motor_drive.enable_flag) |
| | | { |
| | | motor_phasechange(); |