| | |
| | | #ifndef _CLOCK_H_ |
| | | #define _CLOCK_H_ |
| | | #include "stdint.h" |
| | | #define SYSTEM_CLOCK (64000000UL) |
| | | #define SYSTEM_CLOCK (48000000UL) |
| | | void Clock_Config(void); |
| | | void Ostick_config(void); |
| | | void delay_1ms(uint32_t count); |
| | |
| | | void PendSV_Handler(void); |
| | | /* this function handles SysTick exception */ |
| | | void SysTick_Handler(void); |
| | | /* this function handles XTI4-15 exception */ |
| | | void EXTI4_15_IRQHandler(void); |
| | | // /* this function handles XTI4-15 exception */ |
| | | // void EXTI4_15_IRQHandler(void); |
| | | void TIMER2_IRQHandler(void); |
| | | #endif /* GD32E23X_IT_H */ |
| | |
| | | #ifndef MOTOR_H |
| | | #define MOTOR_H |
| | | #include "gpio.h" |
| | | #include "gd32e23x_exti.h" |
| | | /* µç»ú¿ØÐýתʵÏֽṹÌå */ |
| | | |
| | |
| | | /* ÀÛ¼Æ TIM_Period¸öºó²úÉúÒ»¸ö¸üлòÕßÖÐ¶Ï |
| | | µ±¶¨Ê±Æ÷´Ó0¼ÆÊýµ½65535£¬¼´Îª65535´Î£¬ÎªÒ»¸ö¼ÆÊýÖÜÆÚ */ |
| | | #define HALL_PERIOD_COUNT (0xFFFF) |
| | | #define SPEED_PRESCALER_COUNT (6400u) |
| | | #define SPEED_PERIOD_COUNT (300u) |
| | | #define SPEED_PRESCALER_COUNT (4800u) |
| | | #define SPEED_PERIOD_COUNT (30000u) |
| | | /* ͨÓÿØÖƶ¨Ê±Æ÷ʱÖÓÔ´TIMxCLK = HCLK = 64MHz |
| | | É趨¶¨Ê±Æ÷ƵÂÊΪ = TIMxCLK / (SPEED_PRESCALER_COUNT) / SPEED_PERIOD_COUNT = 33.333Hz |
| | | ÖÜÆÚ T = 30ms */ |
| | | #define HALL_PRESCALER_COUNT (110) |
| | | |
| | | #define HALL_A_EXTI (EXTI_4) |
| | | #define HALL_B_EXTI (EXTI_5) |
| | | #define HALL_C_EXTI (EXTI_15) |
| | | #define HALL_C_EXTI (EXTI_5) |
| | | #define HALL_B_EXTI (EXTI_15) |
| | | |
| | | #define MOTOR_OUT_CH_U (TIMER_CH_1) |
| | | #define MOTOR_OUT_CH_V (TIMER_CH_0) |
| | | #define MOTOR_OUT_CH_W (TIMER_CH_2) |
| | | |
| | | #define MOTOR_U_L_ENABLE (gpio_bit_write(PWM_LIN2_PORT, PWM_LIN2_PIN, SET)) |
| | | #define MOTOR_U_L_DISABLE (gpio_bit_write(PWM_LIN2_PORT, PWM_LIN2_PIN, RESET)) |
| | | |
| | | #define MOTOR_V_L_ENABLE (gpio_bit_write(PWM_LIN3_PORT, PWM_LIN3_PIN, SET)) |
| | | #define MOTOR_V_L_DISABLE (gpio_bit_write(PWM_LIN3_PORT, PWM_LIN3_PIN, RESET)) |
| | | |
| | | #define MOTOR_W_L_ENABLE (gpio_bit_write(PWM_LIN1_PORT, PWM_LIN1_PIN, SET)) |
| | | #define MOTOR_W_L_DISABLE (gpio_bit_write(PWM_LIN1_PORT, PWM_LIN1_PIN, RESET)) |
| | | |
| | | extern void HAL_HallExti_TriggerCallback(void); |
| | | extern void BLDC_SpeedAndPID(void); |
| | | extern float get_motor_speed(void); |
| | |
| | | #ifndef _PWM_H_ |
| | | #define _PWM_H_ |
| | | #include "gd32e23x_timer.h" |
| | | //100us * 300 = 30ms |
| | | #define PERIOD_CAP (300U) |
| | | //100us * 30000 = 3s |
| | | #define PERIOD_CAP (30000U) |
| | | |
| | | //64Mzhz / 4000 = 16Khz = 62.5us |
| | | //48Mzhz / 3000 = 16Khz = 62.5us |
| | | #define PERIOD_CMP (4000u) |
| | | |
| | | void TimerInit(void); |
| | |
| | | extern void StartSpeedTime(void); |
| | | extern void StopSpeedTime(void); |
| | | extern void stop_pwm_output(void); |
| | | extern void TIMER2_IRQHandler_CallBack(void); |
| | | extern uint32_t GetSpeedTimerOutcnt(void); |
| | | #endif |
| | |
| | | rcu_osci_on(RCU_IRC8M); //ʹÓÃÄÚ²¿8MRCʱÖÓ |
| | | rcu_osci_stab_wait(RCU_IRC8M); |
| | | rcu_system_clock_source_config(RCU_CKSYSSRC_PLL); //sysclk is PLL |
| | | rcu_pll_config(RCU_PLLSRC_IRC8M_DIV2, RCU_PLL_MUL16); //8MHz/2 =4MHz PLL =4MHz*16 =64MHz |
| | | rcu_ahb_clock_config(RCU_AHB_CKSYS_DIV1); //AHB 64M |
| | | rcu_apb1_clock_config(RCU_APB1_CKAHB_DIV1); //APB1 64M |
| | | rcu_apb2_clock_config(RCU_APB2_CKAHB_DIV1); //APB2 64M |
| | | rcu_adc_clock_config(RCU_ADCCK_APB2_DIV4); //max 14M,current:64/4=16M |
| | | rcu_pll_config(RCU_PLLSRC_IRC8M_DIV2, RCU_PLL_MUL12); //8MHz/2 =4MHz PLL =4MHz*12 =48MHz |
| | | rcu_ahb_clock_config(RCU_AHB_CKSYS_DIV1); //AHB 48M |
| | | rcu_apb1_clock_config(RCU_APB1_CKAHB_DIV1); //APB1 48M |
| | | rcu_apb2_clock_config(RCU_APB2_CKAHB_DIV1); //APB2 48M |
| | | rcu_adc_clock_config(RCU_ADCCK_APB2_DIV4); //max 14M,current:48/4=12M |
| | | rcu_usart_clock_config(RCU_USART0SRC_IRC8M); //USART0 8M |
| | | rcu_rtc_clock_config(RCU_RTCSRC_NONE); |
| | | |
| | |
| | | gpio_mode_set(HALL_SENSOR_A_PORT, GPIO_MODE_INPUT, GPIO_PUPD_NONE, HALL_SENSOR_A_PIN); |
| | | gpio_mode_set(HALL_SENSOR_B_PORT, GPIO_MODE_INPUT, GPIO_PUPD_NONE, HALL_SENSOR_B_PIN); |
| | | gpio_mode_set(HALL_SENSOR_C_PORT, GPIO_MODE_INPUT, GPIO_PUPD_NONE, HALL_SENSOR_C_PIN); |
| | | /* enable the CFGCMP clock */ |
| | | rcu_periph_clock_enable(RCU_CFGCMP); |
| | | nvic_irq_enable(EXTI4_15_IRQn, 0U); |
| | | /* connect EXTI line to GPIO pin */ |
| | | syscfg_exti_line_config(EXTI_SOURCE_GPIOB, EXTI_SOURCE_PIN4); |
| | | syscfg_exti_line_config(EXTI_SOURCE_GPIOB, EXTI_SOURCE_PIN5); |
| | |
| | | gpio_af_set(PWM_HIN3_PORT, GPIO_AF_2, PWM_HIN3_PIN); |
| | | gpio_output_options_set(PWM_HIN3_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, PWM_HIN3_PIN); |
| | | |
| | | gpio_mode_set(PWM_LIN1_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, PWM_LIN1_PIN); |
| | | gpio_af_set(PWM_LIN1_PORT, GPIO_AF_2, PWM_LIN1_PIN); |
| | | gpio_output_options_set(PWM_LIN1_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, PWM_LIN1_PIN); |
| | | // gpio_mode_set(PWM_LIN1_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, PWM_LIN1_PIN); |
| | | // gpio_af_set(PWM_LIN1_PORT, GPIO_AF_2, PWM_LIN1_PIN); |
| | | // gpio_output_options_set(PWM_LIN1_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, PWM_LIN1_PIN); |
| | | |
| | | gpio_mode_set(PWM_LIN2_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, PWM_LIN2_PIN); |
| | | gpio_af_set(PWM_LIN2_PORT, GPIO_AF_2, PWM_LIN2_PIN); |
| | | gpio_output_options_set(PWM_LIN2_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, PWM_LIN2_PIN); |
| | | // gpio_mode_set(PWM_LIN2_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, PWM_LIN2_PIN); |
| | | // gpio_af_set(PWM_LIN2_PORT, GPIO_AF_2, PWM_LIN2_PIN); |
| | | // gpio_output_options_set(PWM_LIN2_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, PWM_LIN2_PIN); |
| | | |
| | | gpio_mode_set(PWM_LIN3_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, PWM_LIN3_PIN); |
| | | gpio_af_set(PWM_LIN3_PORT, GPIO_AF_2, PWM_LIN3_PIN); |
| | | gpio_output_options_set(PWM_LIN3_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, PWM_LIN3_PIN); |
| | | // gpio_mode_set(PWM_LIN3_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, PWM_LIN3_PIN); |
| | | // gpio_af_set(PWM_LIN3_PORT, GPIO_AF_2, PWM_LIN3_PIN); |
| | | // gpio_output_options_set(PWM_LIN3_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, PWM_LIN3_PIN); |
| | | gpio_mode_set(PWM_LIN1_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, PWM_LIN1_PIN); //LIN1 |
| | | gpio_bit_write(PWM_LIN1_PORT, PWM_LIN1_PIN, RESET); |
| | | gpio_mode_set(PWM_LIN2_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, PWM_LIN2_PIN); //LIN2 |
| | | gpio_bit_write(PWM_LIN2_PORT, PWM_LIN2_PIN, RESET); |
| | | gpio_mode_set(PWM_LIN3_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, PWM_LIN3_PIN); //LIN3 |
| | | gpio_bit_write(PWM_LIN3_PORT, PWM_LIN3_PIN, RESET); |
| | | |
| | | //初始化配置SDH2136 |
| | | gpio_mode_set(SDH2136_EN_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, SDH2136_EN_PIN); //EN |
| | |
| | | #include "bldc_ctrl.h" |
| | | #include "pwm.h" |
| | | #include "string.h" |
| | | #include "SEGGER_RTT_Conf.h" |
| | | #include "SEGGER_RTT.h" |
| | | static volatile motor_rotate_t motor_drive = {0}; |
| | | static uint32_t motor_pluse = 0; |
| | | static void motor_phasechange(void); |
| | |
| | | motor_drive.speed = 0; |
| | | motor_drive.enable_flag = 0; |
| | | memset(motor_drive.speed_group, 0, SPEED_FILTER_NUM); |
| | | |
| | | hall_enable(); |
| | | }; |
| | | /** |
| | | * @brief ʹÄÜ»ô¶û´«¸ÐÆ÷ |
| | |
| | | float f = 0; |
| | | |
| | | /* ¼ÆËãËÙ¶È£º |
| | | µç»úÿתһȦ¹²ÓÃ12¸öÂö³å£¬(1.0/(64000000.0/6400)Ϊ¼ÆÊýÆ÷µÄÖÜÆÚ£¬(1.0/(48000000.0/6400) * time)Ϊʱ¼ä³¤¡£ |
| | | µç»úÿתһȦ¹²ÓÃ12¸öÂö³å£¬(1.0/(48000000.0/6400)Ϊ¼ÆÊýÆ÷µÄÖÜÆÚ£¬(1.0/(48000000.0/6400) * time)Ϊʱ¼ä³¤¡£ |
| | | */ |
| | | |
| | | if (time == 0) |
| | | motor_drive.speed_group[count++] = 0; |
| | | else |
| | | { |
| | | f = (1.0f / (64000000.0f / SPEED_PRESCALER_COUNT) * time); |
| | | f = (1.0f / 12.0f) / (f / 60.0f); |
| | | // f = (1.0f / (48000000.0f / SPEED_PRESCALER_COUNT) * time); |
| | | // f = (1.0f / 12.0f) / (f / 60.0f); |
| | | f = time; |
| | | motor_drive.speed_group[count++] = f; |
| | | } |
| | | update_speed_dir(dir_in); |
| | |
| | | */ |
| | | void HAL_HallExti_TriggerCallback(void) |
| | | { |
| | | uint8_t step = 0; |
| | | step = get_hall_state(); |
| | | /* »ñÈ¡»ô¶û´«¸ÐÆ÷Òý½Å״̬,×÷Ϊ»»ÏàµÄÒÀ¾Ý */ |
| | | if (exti_interrupt_flag_get(HALL_A_EXTI | HALL_B_EXTI | HALL_C_EXTI)) // ÅжÏÊÇ·ñÓÉ´¥·¢ÖжϲúÉú |
| | | { |
| | | // update_motor_speed(step, __HAL_TIM_GET_COMPARE(htim, TIM_CHANNEL_1));//TODO Ö÷¶¨Ê±Æ÷´¦»ñµÃ¼ÆÊýʱ¼ä |
| | | update_motor_speed(step, 300u * GetSpeedTimerOutcnt() + timer_counter_read(TIMER2)); |
| | | SEGGER_RTT_printf(0, "Speed is:%d!\n", motor_drive.speed); |
| | | motor_drive.timeout = 0; |
| | | exti_interrupt_flag_clear(HALL_A_EXTI | HALL_B_EXTI | HALL_C_EXTI); |
| | | } |
| | | // if (RESET != exti_interrupt_flag_get(EXTI_4)) |
| | | // { |
| | | // SEGGER_RTT_printf(0, "HALL_A_EXTI triggle!\n"); |
| | | // } |
| | | // else if (RESET != exti_interrupt_flag_get(EXTI_5)) |
| | | // { |
| | | // SEGGER_RTT_printf(0, "HALL_C_EXTI triggle!\n"); |
| | | // } |
| | | // else if (RESET != exti_interrupt_flag_get(EXTI_15)) |
| | | // { |
| | | // SEGGER_RTT_printf(0, "HALL_B_EXTI triggle!\n"); |
| | | // } |
| | | motor_phasechange(); |
| | | // HAL_TIM_GenerateEvent(&htimx_bldcm, TIM_EVENTSOURCE_COM); // Èí¼þ²úÉú»»Ïàʼþ£¬´Ëʱ²Å½«ÅäÖÃдÈë |
| | | } |
| | |
| | | /* channel U configuration */ |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_U, TIMER_OC_MODE_PWM1); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCX_ENABLE); |
| | | timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCXN_DISABLE); |
| | | MOTOR_U_L_DISABLE; |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCXN_DISABLE); |
| | | |
| | | /* channel V configuration */ |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCX_DISABLE); |
| | | timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCXN_DISABLE); |
| | | MOTOR_V_L_DISABLE; |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCXN_DISABLE); |
| | | |
| | | /* channel W configuration */ |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_W, TIMER_OC_MODE_PWM1); |
| | | // timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_W, TIMER_OC_MODE_PWM1); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCX_DISABLE); |
| | | timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCXN_ENABLE); |
| | | MOTOR_W_L_ENABLE; |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCXN_ENABLE); |
| | | |
| | | step++; |
| | | break; |
| | |
| | | /* channel U configuration */ |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCX_DISABLE); |
| | | timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCXN_DISABLE); |
| | | MOTOR_U_L_DISABLE; |
| | | |
| | | /* channel V configuration */ |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_V, TIMER_OC_MODE_PWM1); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCX_ENABLE); |
| | | timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCXN_DISABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCXN_DISABLE); |
| | | MOTOR_V_L_DISABLE; |
| | | |
| | | /* channel W configuration */ |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_W, TIMER_OC_MODE_PWM1); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCX_DISABLE); |
| | | timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCXN_ENABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCXN_ENABLE); |
| | | MOTOR_W_L_ENABLE; |
| | | |
| | | step++; |
| | | break; |
| | |
| | | /* channel U configuration */ |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_U, TIMER_OC_MODE_PWM1); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCX_DISABLE); |
| | | timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCXN_ENABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCXN_ENABLE); |
| | | MOTOR_U_L_ENABLE; |
| | | |
| | | /* channel V configuration */ |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_V, TIMER_OC_MODE_PWM1); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCX_ENABLE); |
| | | timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCXN_DISABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCXN_DISABLE); |
| | | MOTOR_V_L_DISABLE; |
| | | |
| | | /* channel W configuration */ |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCX_DISABLE); |
| | | timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCXN_DISABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCXN_DISABLE); |
| | | MOTOR_W_L_DISABLE; |
| | | |
| | | step++; |
| | | break; |
| | |
| | | /* channel U configuration */ |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_U, TIMER_OC_MODE_PWM1); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCX_DISABLE); |
| | | timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCXN_ENABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCXN_ENABLE); |
| | | MOTOR_U_L_ENABLE; |
| | | |
| | | /* channel V configuration */ |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCX_DISABLE); |
| | | timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCXN_DISABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCXN_DISABLE); |
| | | MOTOR_V_L_DISABLE; |
| | | |
| | | /* channel W configuration */ |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_W, TIMER_OC_MODE_PWM1); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCX_ENABLE); |
| | | timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCXN_DISABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCXN_DISABLE); |
| | | MOTOR_W_L_DISABLE; |
| | | |
| | | step++; |
| | | break; |
| | |
| | | case 5: |
| | | /* channel U configuration */ |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCX_DISABLE); |
| | | timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCXN_DISABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCXN_DISABLE); |
| | | MOTOR_U_L_DISABLE; |
| | | |
| | | /* channel V configuration */ |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_V, TIMER_OC_MODE_PWM1); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCX_DISABLE); |
| | | timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCXN_ENABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCXN_ENABLE); |
| | | MOTOR_V_L_ENABLE; |
| | | |
| | | /* channel W configuration */ |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_W, TIMER_OC_MODE_PWM1); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCX_ENABLE); |
| | | timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCXN_DISABLE); |
| | | |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCXN_DISABLE); |
| | | MOTOR_W_L_DISABLE; |
| | | step++; |
| | | break; |
| | | |
| | |
| | | /* channel U configuration */ |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_U, TIMER_OC_MODE_PWM1); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCX_ENABLE); |
| | | timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCXN_DISABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_U, TIMER_CCXN_DISABLE); |
| | | MOTOR_U_L_DISABLE; |
| | | |
| | | /* channel V configuration */ |
| | | timer_channel_output_mode_config(TIMER0, MOTOR_OUT_CH_V, TIMER_OC_MODE_PWM1); |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCX_DISABLE); |
| | | timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCXN_ENABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_V, TIMER_CCXN_ENABLE); |
| | | MOTOR_V_L_ENABLE; |
| | | |
| | | /* channel W configuration */ |
| | | timer_channel_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCX_DISABLE); |
| | | timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCXN_DISABLE); |
| | | // timer_channel_complementary_output_state_config(TIMER0, MOTOR_OUT_CH_W, TIMER_CCXN_DISABLE); |
| | | MOTOR_W_L_DISABLE; |
| | | |
| | | step = 1; |
| | | break; |
| | |
| | | |
| | | #include "gd32e23x_it.h" |
| | | #include "motor.h" |
| | | #include "pwm.h" |
| | | #include "os_task.h" |
| | | |
| | | /*! |
| | |
| | | { |
| | | if (SET == timer_interrupt_flag_get(TIMER2, TIMER_INT_FLAG_UP)) //time2 count up overflow |
| | | { |
| | | BLDC_SpeedAndPID(); |
| | | // BLDC_SpeedAndPID(); |
| | | TIMER2_IRQHandler_CallBack(); |
| | | timer_interrupt_flag_clear(TIMER2, TIMER_INT_FLAG_UP); |
| | | } |
| | | } |
| | |
| | | * |
| | | */ |
| | | #include "pwm.h" |
| | | |
| | | static volatile uint32_t timer_outcnt = 0; |
| | | /***************************************************************************************************** |
| | | Timer2 is used to speed cal |
| | | APB1 is 64M ,so Timer2 clock is 64M,after prescaler 480 is 0.1M(10us) |
| | |
| | | |
| | | timer_deinit(TIMER2); |
| | | |
| | | timercontralcfg.prescaler = 6399; //64Mhz /6400 =0.01Mhz = 100us |
| | | timercontralcfg.prescaler = 4799; //48Mhz /4800 =0.01Mhz = 100us |
| | | timercontralcfg.alignedmode = TIMER_COUNTER_EDGE; |
| | | timercontralcfg.counterdirection = TIMER_COUNTER_UP; |
| | | timercontralcfg.period = PERIOD_CAP; //100us*10000=1s |
| | |
| | | *****************************************************************************************************/ |
| | | static void Timer0Init(void) |
| | | { |
| | | uint16_t Duty = PERIOD_CMP + 1; |
| | | uint16_t Duty = PERIOD_CMP / 10; |
| | | timer_parameter_struct timercontralcfg; |
| | | timer_oc_parameter_struct timeroutcfg[3]; |
| | | timer_break_parameter_struct timer_breakpara; |
| | |
| | | |
| | | timeroutcfg[0].ocpolarity = TIMER_OC_POLARITY_HIGH; //channel output polarity is high |
| | | timeroutcfg[0].ocnpolarity = TIMER_OCN_POLARITY_HIGH; |
| | | timeroutcfg[0].outputstate = TIMER_CCX_ENABLE; //channel enable |
| | | timeroutcfg[0].outputnstate = TIMER_CCXN_ENABLE; //channel complementary enable |
| | | timeroutcfg[0].outputstate = TIMER_CCX_ENABLE; //channel enable |
| | | timeroutcfg[0].outputnstate = TIMER_CCXN_DISABLE; //channel complementary DISABLE |
| | | timeroutcfg[0].ocidlestate = TIMER_OC_IDLE_STATE_LOW; |
| | | timeroutcfg[0].ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; |
| | | |
| | | timeroutcfg[1].ocpolarity = TIMER_OC_POLARITY_HIGH; //channel output polarity is high |
| | | timeroutcfg[1].ocnpolarity = TIMER_OCN_POLARITY_HIGH; |
| | | timeroutcfg[1].outputstate = TIMER_CCX_ENABLE; //channel enable |
| | | timeroutcfg[1].outputnstate = TIMER_CCXN_ENABLE; //channel complementary enable |
| | | timeroutcfg[1].outputstate = TIMER_CCX_ENABLE; //channel enable |
| | | timeroutcfg[1].outputnstate = TIMER_CCXN_DISABLE; //channel complementary DISABLE |
| | | timeroutcfg[1].ocidlestate = TIMER_OC_IDLE_STATE_LOW; |
| | | timeroutcfg[1].ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; |
| | | |
| | | timeroutcfg[2].ocpolarity = TIMER_OC_POLARITY_HIGH; //channel output polarity is high |
| | | timeroutcfg[2].ocnpolarity = TIMER_OCN_POLARITY_HIGH; |
| | | timeroutcfg[2].outputstate = TIMER_CCX_ENABLE; //channel enable |
| | | timeroutcfg[2].outputnstate = TIMER_CCXN_ENABLE; //channel complementary enable |
| | | timeroutcfg[2].outputstate = TIMER_CCX_ENABLE; //channel enable |
| | | timeroutcfg[2].outputnstate = TIMER_CCXN_DISABLE; //channel complementary DISABLE |
| | | timeroutcfg[2].ocidlestate = TIMER_OC_IDLE_STATE_LOW; |
| | | timeroutcfg[2].ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; |
| | | |
| | |
| | | |
| | | void TimerInit(void) |
| | | { |
| | | // rcu_periph_clock_enable(RCU_TIMER2); |
| | | rcu_periph_clock_enable(RCU_TIMER2); |
| | | rcu_periph_clock_enable(RCU_TIMER0); |
| | | Timer0Init(); |
| | | Timer2Init(); |
| | |
| | | { |
| | | timer_disable(TIMER2); |
| | | } |
| | | extern void TIMER2_IRQHandler_CallBack(void) |
| | | { |
| | | timer_outcnt++; |
| | | } |
| | | |
| | | extern uint32_t GetSpeedTimerOutcnt(void) |
| | | { |
| | | uint32_t rtn = timer_outcnt; |
| | | timer_outcnt = 0; |
| | | return rtn; |
| | | } |