From bc6c916bff0b8d342c1cd62da73a2a09f18d22a8 Mon Sep 17 00:00:00 2001
From: tao_z <tzj0429@163.com>
Date: Thu, 24 Jun 2021 22:22:49 +0800
Subject: [PATCH] 基本模块编译通过
---
USR/SRC/Clock.c | 10 +++++-----
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/USR/SRC/Clock.c b/USR/SRC/Clock.c
index 3f842de..c84e682 100644
--- a/USR/SRC/Clock.c
+++ b/USR/SRC/Clock.c
@@ -12,11 +12,11 @@
rcu_osci_on(RCU_IRC8M); //ʹ���ڲ�8MRCʱ��
rcu_osci_stab_wait(RCU_IRC8M);
rcu_system_clock_source_config(RCU_CKSYSSRC_PLL); //sysclk is PLL
- rcu_pll_config(RCU_PLLSRC_IRC8M_DIV2, RCU_PLL_MUL12); //8MHz/2 =4MHz PLL =4MHz*12 =48MHz
- rcu_ahb_clock_config(RCU_AHB_CKSYS_DIV1); //AHB 48M
- rcu_apb1_clock_config(RCU_APB1_CKAHB_DIV1); //APB1 48M
- rcu_apb2_clock_config(RCU_APB2_CKAHB_DIV1); //APB2 48M
- rcu_adc_clock_config(RCU_ADCCK_APB2_DIV4); //max 14M,current:12M
+ rcu_pll_config(RCU_PLLSRC_IRC8M_DIV2, RCU_PLL_MUL16); //8MHz/2 =4MHz PLL =4MHz*16 =64MHz
+ rcu_ahb_clock_config(RCU_AHB_CKSYS_DIV1); //AHB 64M
+ rcu_apb1_clock_config(RCU_APB1_CKAHB_DIV1); //APB1 64M
+ rcu_apb2_clock_config(RCU_APB2_CKAHB_DIV1); //APB2 64M
+ rcu_adc_clock_config(RCU_ADCCK_APB2_DIV4); //max 14M,current:64/4=16M
rcu_usart_clock_config(RCU_USART0SRC_IRC8M); //USART0 8M
rcu_rtc_clock_config(RCU_RTCSRC_NONE);
--
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