/**
  ******************************************************************************
  * @file     xl_adc.h
  * @author   software group
  * @brief    This file contains all the functions prototypes for the ADC 
  *           firmware library.
  ******************************************************************************
  * @attention
	*
  * 2019 by Chipways Communications,Inc. All Rights Reserved.
  * This software is supplied under the terms of a license
  * agreement or non-disclosure agreement with Chipways.
  * Passing on and copying of this document,and communication
  * of its contents is not permitted without prior written
  * authorization.
  *
  * <h2><center>&copy; COPYRIGHT 2019 Chipways</center></h2>
  ******************************************************************************
  */
#ifndef XL_ADC_H__
#define XL_ADC_H__

#ifdef __cplusplus
extern "C" {
#endif
	
/* Includes ---------------------------------------------------------------*/
#include "XL6600.h"
	
	
/* Register define ------------------------------------------------------------*/
/* CR Bit Fields */
#define ADC_CR_MODE_MASK                        0x3u
#define ADC_CR_MODE_SHIFT                       0

#define ADC_CR_FSE_MASK                         0x4u
#define ADC_CR_FSE_SHIFT                        2

#define ADC_CR_FDEP_MASK                        0x38u
#define ADC_CR_FDEP_SHIFT                       3

#define ADC_CR_CCE_MASK                         0x40u
#define ADC_CR_CCE_SHIFT                        6

#define ADC_CR_AIE_MASK                         0x80u
#define ADC_CR_AIE_SHIFT                        7

#define ADC_CR_TRGSEL_MASK                      0x100u
#define ADC_CR_TRGSEL_SHIFT                     8

#define ADC_CR_COSBEN_MASK                      0x200u
#define ADC_CR_COSBEN_SHIFT                     9

#define ADC_CR_LPE_MASK                         0x400u
#define ADC_CR_LPE_SHIFT                        10

#define ADC_CR_LSTE_MASK                        0x800u
#define ADC_CR_LSTE_SHIFT                       11

#define ADC_CR_REFSEL_MASK                      0x3000u
#define ADC_CR_REFSEL_SHIFT                     12

#define ADC_CR_CLKSEL_MASK                      0xC000u
#define ADC_CR_CLKSEL_SHIFT                     14

#define ADC_CR_CFE_MASK                         0x10000u
#define ADC_CR_CFE_SHIFT                        16

#define ADC_CR_CFRE_MASK                        0x20000u
#define ADC_CR_CFRE_SHIFT                       17

#define ADC_CR_CFGRE_MASK                       0x40000u
#define ADC_CR_CFGRE_SHIFT                      18

#define ADC_CR_CFSEL_MASK                       0x80000u
#define ADC_CR_CFSEL_SHIFT                      19

#define ADC_CR_ADACKS_MASK                      0x100000u
#define ADC_CR_ADACKS_SHIFT                     20

#define ADC_CR_ECOBD_MASK                      0x200000u
#define ADC_CR_ECOBD_SHIFT                     21

#define ADC_CR_DMATXEN_MASK                     0x400000u
#define ADC_CR_DMATXEN_SHIFT                    22

#define ADC_CR_DMARXEN_MASK                     0x800000u
#define ADC_CR_DMARXEN_SHIFT                    23

#define ADC_CR_ADIV_MASK                        0x3000000u
#define ADC_CR_ADIV_SHIFT                       24

/* SR Bit Fields */
#define ADC_SR_RFCNT_MASK                       0xFu
#define ADC_SR_RFCNT_SHIFT                      0

#define ADC_SR_RFF_MASK                         0x10u
#define ADC_SR_RFF_SHIFT                        4

#define ADC_SR_REF_MASK                         0x20u
#define ADC_SR_REF_SHIFT                        5

#define ADC_SR_CCF_MASK                         0x80u
#define ADC_SR_CCF_SHIFT                        7

#define ADC_SR_CB_MASK                          0x100u
#define ADC_SR_CB_SHIFT                         8

#define ADC_SR_CFF_MASK                         0x200u
#define ADC_SR_CFF_SHIFT                        9

#define ADC_SR_CEF_MASK                         0x400u
#define ADC_SR_CEF_SHIFT                        10

/* CSR Bit Fields */
#define ADC_CSR_ADCH_MASK                       0x1Fu
#define ADC_CSR_ADCH_SHIFT                      0
/* RDR Bit Fields */
#define ADC_RDR_DATA_MASK                       0xFFFu
#define ADC_RDR_DATA_SHIFT                      0
/* CVR Bit Fields */
#define ADC_CVR_CVL_MASK                        0xFFFu
#define ADC_CVR_CVL_SHIFT                       0

#define ADC_CVR_CVH_MASK                        0xFFF0000u
#define ADC_CVR_CVH_SHIFT                       16
/* EHTMR Bit Fields */
#define ADC_EHTMR_EN_MASK                       0x1u
#define ADC_EHTMR_EN_SHIFT                      0

#define ADC_EHTMR_HTRGM_MASK                    0x2u
#define ADC_EHTMR_HTRGM_SHIFT                   1
/* APCTL Bit Fields */
#define ADC_PINSEL_ADPC_MASK                    0xFFFFFFu
#define ADC_PINSEL_ADPC_SHIFT                   0


/** ADC - Register Layout Typedef */
typedef struct {
  __IO uint32_t CR;                               /*!< ADC¿ØÖƼĴæÆ÷, offset: 0x0 */
  __I  uint32_t SR;                               /*!< ADC״̬¼Ä´æÆ÷, offset: 0x4 */
  __IO uint32_t CSR;                              /*!< Êý¾ÝͨµÀÑ¡Ôñ¼Ä´æÆ÷, offset: 0x8 */
  __I  uint32_t RDR;                              /*!< ת»»½á¹ûÊä³ö¼Ä´æÆ÷, offset: 0xC */
  __IO uint32_t CVR;                              /*!< ת»»½á¹û±È½Ï±ê×¼Öµ¼Ä´æÆ÷, offset: 0x10 */
  __IO uint32_t EHTMR;                            /*!< ADCʹÄÜÓë´¥·¢¿ØÖƼĴæÆ÷, offset: 0x14 */   
  __IO uint32_t APCTL;                            /*!< ADCʹÄÜÓë´¥·¢¿ØÖƼĴæÆ÷, offset: 0x18 */
  __IO uint32_t CFR;                              /*!< ADC±È½Ï¹¦ÄÜ״̬¼Ä´æÆ÷, offset: 0x1C */
} ADC_Type, *ADC_MemMapPtr;
extern ADC_Type* ADC0;



/** @addtogroup XL6600_StdPeriph_Driver
  * @{
  */

/** @addtogroup ADC 
  * @{
  */


/* Exported types ------------------------------------------------------------*/ 

/**
 * @brief ADC ³õʼ»¯½á¹¹Ì嶨Òå
 */
typedef struct
{
  uint32_t ADC_Mode;                       /*!< ÅäÖÃADCת»»Êý¾Ý¿í¶È */
                                                
  uint32_t ADC_ReferVoltage;               /*!< ת»»²Î¿¼µçѹԴ */
	
  uint32_t ADC_ClockSource;                /*!< ADCת»»Ê±ÖÓÔ´ */
	
  uint32_t ADC_ClkDivide;                  /*!< ADCת»»Ê±ÖÓ·ÖƵϵÊý */

  FunctionalState ADC_LowPowerConvert;     /*!< ADCµÍ¹¦ºÄת»»Ê¹ÄÜ,ÉèÖóÉENABLE»òÕßDISABLE */
                                               

  FunctionalState ADC_LongTimeConvert;     /*!< ADC³¤²ÉÑùʱ¼äʹÄÜ, ÉèÖóÉENABLE»òÕßDISABLE */
                                              

}ADC_InitTypeDef;


/**
  * @brief ADC_FIFO³õʼ»¯½á¹¹Ì嶨Òå
  */
typedef struct
{
  uint32_t ADC_FIFOLevel;                   /*!< FIFO Éî¶È */                                              
	
  FunctionalState ADC_ChannelScan;          /*!< ADCÐŵÀɨÃ蹦ÄÜʹÄÜ, ÉèÖóÉENABLE»òÕßDISABLE */
                                              
}ADC_FIFOTypeDef;


/**
  * @brief ADC±È½ÏÆ÷³õʼ»¯½á¹¹Ì嶨Òå
  */
typedef struct
{
	uint32_t ADC_CompareMode;                 /*!< ADC±È½Ï·½Ê½ £¬´óС»ò·¶Î§±È½Ï */
											   
	uint32_t ADC_CompareOut;                  /*!< ADC±È½ÏÊä³öģʽ */

	uint32_t ADC_FIFOCompareOut;              /*!< ADC FIFO ±È½ÏÊä³öģʽ */

	uint32_t ADC_CompareValueHigh;            /*!< ±È½ÏֵΪ¸ß */

	uint32_t ADC_CompareValueLow;             /*!< ±È½ÏֵΪµÍ */

	FunctionalState ADC_AutoCompare;          /*!< ×Ô¶¯±È½Ï¹¦ÄÜʹÄÜ,ÉèÖóÉENABLE»òÕßDISABLE */
	
	FunctionalState ADC_CompareResultSwitch;  /*!< ±È½Ï½á¹ûת»»,ÉèÖóÉENABLE»òÕßDISABLE */

}ADC_CompareTypeDef;

/* Exported constants --------------------------------------------------------*/
/** @defgroup ADC_Exported_Constants ADCÄ£¿éʹÓòÎÊý¶¨Òå
  * @{
  */

/**
	* @defgroup ADC_Mode_list ADCģʽ¶¨Òå
	* @{
	*/
#define ADC_MODE_8BIT									  		0x0		/*!< 8λÊä³öģʽ */
#define ADC_MODE_10BIT											0x1		/*!< 10λÊä³öģʽ */
#define ADC_MODE_12BIT											0x2		/*!< 12λÊä³öģʽ */
/**
	* @}
	*/

/**
	* @defgroup ADC_FIFO_list ADCFIFOÉî¶È¶¨Òå
	* @{
	*/	
#define ADC_FIFO_DISABLE                		0     /*!< FIFO¹¦ÄÜ¹Ø±Õ */
#define ADC_FIFO_LEVEL2                 		1     /*!< FIFOÉî¶ÈΪ2 */
#define ADC_FIFO_LEVEL3                 		2     /*!< FIFOÉî¶ÈΪ3 */
#define ADC_FIFO_LEVEL4                 		3     /*!< FIFOÉî¶ÈΪ4 */
#define ADC_FIFO_LEVEL5                 		4     /*!< FIFOÉî¶ÈΪ5 */
#define ADC_FIFO_LEVEL6                 		5     /*!< FIFOÉî¶ÈΪ6 */
#define ADC_FIFO_LEVEL7                 		6     /*!< FIFOÉî¶ÈΪ7 */
#define ADC_FIFO_LEVEL8                 		7	    /*!< FIFOÉî¶ÈΪ8 */
/**
	* @}
	*/
	
/**
	* @defgroup ADC_CONTINUOUS_list ADCת»»Ä£Ê½¶¨Òå
	* @{
	*/
#define ADC_CONVENTION_ONCE              		0x00u   /*!< µ¥´Îת»» */
#define ADC_CONVENTION_CONTINUOUS        		0x01u   /*!< Á¬Ðøת»» */
/**
	* @}
	*/
	
/**
	* @defgroup ADC_Trigger_List ADC´¥·¢Ä£Ê½Ñ¡Ôñ
	* @{
	*/
#define ADC_SOFTWARE_TRIGGER             		0x00u   /*!< Èí¼þ´¥·¢ */
#define ADC_HARDWARE_TRIGGER             		0x01u   /*!< Ó²¼þ´¥·¢ */
/**
	* @}
	*/

/**
	* @defgroup ADC_VRFF_List ADC²Î¿¼µçѹ¶¨Òå
	* @{
	*/
#define ADC_VREF_VREFH                   		0x00		/*!< ²Î¿¼µçѹÊÇVREFH */
#define ADC_VREF_VDDA                    		0x01		/*!< ²Î¿¼µçѹÊÇVDDA */
/**
	* @}
	*/
	

	
/**
	* @defgroup ADC_ClockSource_list ADCʱÖÓÔ´¶¨Òå
	* @{
	*/
#define ADC_CLOCK_BUS_CLOCK							 		0x00	              /*!< ADCʱÖÓÔ´ÊÇ×ÜÏßʱÖÓ */
#define ADC_CLOCK_BUS_CLOCK_DIVIDE_2	   		            0x01	  /*!< ADCʱÖÓÔ´ÊÇ×ÜÏßʱÖÓ2·ÖƵ */
#define ADC_CLOCK_ALTCLK							   		0x02	              /*!< ADCʱÖÓÔ´ÊDZ¸ÓÃʱÖÓ(ALTCLK) */
#define ADC_CLOCK_ADACK								   		0x03	              /*!< ADCʱÖÓÔ´ÊÇÒ첽ʱÖÓ(ADACK) */
/**
	* @}
	*/
	
/**
	* @defgroup ADC_CPMPARE_List ADC±È½Ïģʽ¶¨Òå
	* @{
	*/	
#define ADC_COMPAREMODE_SIZE              	0x00   /*!< ADC´óС±È½Ï */
#define ADC_COMPAREMODE_RANGE             	0x01   /*!< ADC·¶Î§±È½Ï */
/**
	* @}
	*/

/**
	* @defgroup ADC_CPMPARE_out_list ADC±È½ÏÊä³öģʽ¶¨Òå
	* @{
	*/	
#define ADC_COMPAREOUT_LESS              		0x00   /*!< СÓÚµÈÓÚ»òÕßÔÚ·¶Î§ÄÚÊä³öת»»½á¹û */
#define ADC_COMPAREOUT_MORE              		0x01   /*!<  ´óÓÚ»òÕßÔÚ·¶Î§ÍâÊä³öת»»½á¹û */
/**
	* @}
	*/

/** 
	* @defgroup ADC_OutputSelect_List ADC±È½ÏÊä³öÊý¾Ýģʽ¶¨Òå
	* @{
	*/	
#define ADC_COMPAREFIFO_ALL              		0x00   /*!< µ±ËùÓÐͨµÀ¶¼Âú×ã±È½Ï½á¹ûʱ£¬Êä³ö±¾´ÎɨÃè½á¹û */
#define ADC_COMPAREFIFO_ONE              		0x01   /*!< ֻҪijһ¸öͨµÀÂú×ã±È½Ï½á¹ûʱ£¬Êä³ö±¾´ÎɨÃè½á¹û */
/**
	* @}
	*/
	
/**
	* @defgroup ADC_AsynchronousClk_Select_List ADCÒ첽ʱÖÓÑ¡Ôñ¶¨Òå
	* @{
	*/	
#define ADC_ADACK_NORMAL                   0x00u   /*!< ADCÒ첽ʱÖÓʹÓñê׼ƵÂÊ */
#define ADC_ADACK_TIMES1P5                 0x01u   /*!< ADCÒ첽ʱÖÓʹÓÃ1.5±¶±ê׼ƵÂÊ */
/**
	* @}
	*/
	
/**
	* @defgroup ADC_Deivied_List ADCʱÖÓ·ÖƵѡÔñ
	* @{
	*/		
#define ADC_ADIV_DIVIDE_1							   		0x00		/*!< ʱÖÓ1·ÖƵ */
#define ADC_ADIV_DIVIDE_2								 		0x01		/*!< ʱÖÓ2·ÖƵ */
#define ADC_ADIV_DIVIDE_4								 		0x02		/*!< ʱÖÓ4·ÖƵ */
#define ADC_ADIV_DIVIDE_8								 		0x03		/*!< ʱÖÓ8·ÖƵ */
/**
	* @}
	*/
	
/**
	* @defgroup ADC_Flags_Definition ADC±È½Ï¹¦ÄÜ״̬±êÖ¾¶¨Òå
	* @{
	*/
#define ADC_FLAG_DATAFIFO_FULL           		0x10     /*!< FIFOÊý¾ÝÂú±êÖ¾ */
#define ADC_FLAG_DATAFIFO_EMPTY          		0x20     /*!< FIFOÊý¾Ý¿Õ±êÖ¾ */
#define ADC_FLAG_CONV_FINISH             		0x80     /*!< ADCת»»½áÊø±êÖ¾ */
#define ADC_FLAG_CONV_BUSY               		0x100    /*!< ADCת»»·±Ã¦±êÖ¾ */
#define ADC_FLAG_ChannelFIFO_FULL        		0x200    /*!< Channel FIFOÊý¾ÝÂú±êÖ¾ */
#define ADC_FLAG_ChannelFIFO_EMPTY       		0x400    /*!< Channel FIFOÊý¾Ý¿Õ±êÖ¾ */
/**
	* @}
	*/

/**
	* @defgroup ADC_COMPARE_FLAGs_Definition ADC±êÖ¾¶¨Òå
	* @{
	*/
#define ADC_CHANNEL0_COMPARE_EXCEPTION			0x000001			/*!< ͨµÀ0±È½Ï½á¹ûÒì³£±êÖ¾ */
#define ADC_CHANNEL1_COMPARE_EXCEPTION			0x000002			/*!< ͨµÀ1±È½Ï½á¹ûÒì³£±êÖ¾ */
#define ADC_CHANNEL2_COMPARE_EXCEPTION			0x000004			/*!< ͨµÀ2±È½Ï½á¹ûÒì³£±êÖ¾ */
#define ADC_CHANNEL3_COMPARE_EXCEPTION			0x000008			/*!< ͨµÀ3±È½Ï½á¹ûÒì³£±êÖ¾ */
#define ADC_CHANNEL4_COMPARE_EXCEPTION			0x000010			/*!< ͨµÀ4±È½Ï½á¹ûÒì³£±êÖ¾ */
#define ADC_CHANNEL5_COMPARE_EXCEPTION			0x000020			/*!< ͨµÀ5±È½Ï½á¹ûÒì³£±êÖ¾ */
#define ADC_CHANNEL6_COMPARE_EXCEPTION			0x000040			/*!< ͨµÀ6±È½Ï½á¹ûÒì³£±êÖ¾ */
#define ADC_CHANNEL7_COMPARE_EXCEPTION			0x000080			/*!< ͨµÀ7±È½Ï½á¹ûÒì³£±êÖ¾ */
#define ADC_CHANNELALL_COMPARE_EXCEPTION		0x000100			/*!< ËùÓÐͨµÀ±È½Ï½á¹ûÒì³£±êÖ¾ */
#define ADC_COMPARE_CFSEL_FLAG					0x010000			    /*!< Êä³ö½á¹ûÑ¡Ôñ·½Ê½±êÖ¾ */
#define ADC_COMPARE_CFGRE_FLAG					0x020000			    /*!< ´óÓÚÑ¡Ôñ±êÖ¾ */
#define ADC_COMPARE_CFRE_FLAG					0x040000			      /*!< ±È½Ï·½Ê½Ñ¡Ôñ±êÖ¾ */
#define ADC_COMPARE_CFE_FLAG					0x080000			      /*!< ×Ô¶¯±È½Ï¹¦ÄÜʹÄܱêÖ¾ */
/**
	* @}
	*/


/**
	* @defgroup ADC_Channel_list ADCͨµÀÑ¡Ôñ¶¨Òå
	* @{
	*/
#define ADC_CHANNEL_AD0                  		0x0     /*!< ADCÊäÈëͨµÀ0 */
#define ADC_CHANNEL_AD1                  		0x1     /*!< ADCÊäÈëͨµÀ1 */
#define ADC_CHANNEL_AD2                  		0x2     /*!< ADCÊäÈëͨµÀ2 */
#define ADC_CHANNEL_AD3                  		0x3     /*!< ADCÊäÈëͨµÀ3 */
#define ADC_CHANNEL_AD4                  		0x4     /*!< ADCÊäÈëͨµÀ4 */
#define ADC_CHANNEL_AD5                  		0x5     /*!< ADCÊäÈëͨµÀ5 */
#define ADC_CHANNEL_AD6                  		0x6     /*!< ADCÊäÈëͨµÀ6 */
#define ADC_CHANNEL_AD7                  		0x7     /*!< ADCÊäÈëͨµÀ7 */
#define ADC_CHANNEL_AD8                  		0x8     /*!< ADCÊäÈëͨµÀ8 */
#define ADC_CHANNEL_AD9                  		0x9     /*!< ADCÊäÈëͨµÀ9 */
#define ADC_CHANNEL_AD10                 		0xa     /*!< ADCÊäÈëͨµÀ10 */
#define ADC_CHANNEL_AD11                 		0xb     /*!< ADCÊäÈëͨµÀ11 */
#define ADC_CHANNEL_AD12                 		0xc     /*!< ADCÊäÈëͨµÀ12 */
#define ADC_CHANNEL_AD13                 		0xd     /*!< ADCÊäÈëͨµÀ13 */
#define ADC_CHANNEL_AD14                 		0xe     /*!< ADCÊäÈëͨµÀ14 */
#define ADC_CHANNEL_AD15                 		0xf     /*!< ADCÊäÈëͨµÀ15 */
#define ADC_CHANNEL_AD16                 		0x10    /*!< ADCÊäÈëͨµÀ16 */
#define ADC_CHANNEL_AD17                 		0x11    /*!< ADCÊäÈëͨµÀ17 */
#define ADC_CHANNEL_AD18                 		0x12    /*!< ADCÊäÈëͨµÀ18 */
#define ADC_CHANNEL_AD19                 		0x13    /*!< ADCÊäÈëͨµÀ19 */
#define ADC_CHANNEL_AD20                 		0x14    /*!< ADCÊäÈëͨµÀ20 */ 
#define ADC_CHANNEL_AD21                 		0x15    /*!< ADCÊäÈëͨµÀ21 */ 
#define ADC_CHANNEL_TEMPSENSOR           		0x16    /*!< ADCÊäÈëͨµÀÄÚ²¿Î¶ȴ«¸ÐÆ÷ */
#define ADC_CHANNEL_BANDGAP              		0x17    /*!< ADC²ÉÑù»ù×¼µçѹ */ 
#define ADC_CHANNEL_AD22                 		0x18    /*!< ADCÊäÈëͨµÀ22 */ 
#define ADC_CHANNEL_AD23                 		0x19    /*!< ADCÊäÈëͨµÀ23 */ 
#define ADC_CHANNEL_VSS                  		0x1A    /*!< ADCÊäÈëͨµÀVSS */ 
#define ADC_CHANNEL_VREFH                		0x1D    /*!< ADCÊäÈëͨµÀVrefh */ 
#define ADC_CHANNEL_VREFL                		0x1E    /*!< ADCÊäÈëͨµÀVrefl */ 
#define ADC_CHANNEL_DISABLE              		0x1F    /*!< ADCʧÄÜ */
/**
	* @}
	*/

/**
  * @}
  */

/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/ 
void ADC_DeInit(ADC_Type* ADCx);
void ADC_Init(ADC_Type* ADCx, const ADC_InitTypeDef* ADC_InitStruct);
void ADC_FIFOConfig(ADC_Type* ADCx, const ADC_FIFOTypeDef* ADC_FIFOStruct);
void ADC_CompareConfig(ADC_Type* ADCx, const ADC_CompareTypeDef* ADC_CompareStruct);
void ADC_EnableCmd(ADC_Type* ADCx, FunctionalState NewState);
void ADC_HardwareTriggrMaskCmd(ADC_Type* ADCx, FunctionalState NewState);
void ADC_SetTriggerMode(ADC_Type* ADCx, uint8_t ADC_Triggermode);
void ADC_ADACKSelect(ADC_Type* ADCx, uint8_t ADC_ADACKmode);
void ADC_SetConventionMode(ADC_Type* ADCx, uint8_t ADC_ConventionMode);
void ADC_SetChannel(ADC_Type* ADCx, uint8_t channelno);
void ADC_InterruptEn(ADC_Type* ADCx, FunctionalState NewState);
void ADC_DMATxEn(ADC_Type* ADCx, FunctionalState NewState);
void ADC_DMARxEn(ADC_Type* ADCx, FunctionalState NewState);
uint16_t ADC_GetConversionValue(const ADC_Type* ADCx);
uint16_t ADC_GetFIFOValueCounter(const ADC_Type* ADCx);
FlagStatus ADC_GetFlagStatus(const ADC_Type* ADCx, uint16_t ADC_FLAG);
FlagStatus ADC_GetCompareFlagStatus(const ADC_Type* ADCx, uint16_t ADC_COMPARE_FLAG);
void ADC_DisableChannelDigFuc(ADC_Type* ADCx, uint8_t channelno, FunctionalState NewState);


#ifdef __cplusplus
}
#endif

#endif    /*__XL_ADC_H__ */
/**
  * @}
  */

/**
  * @}
  */