/** ****************************************************************************** * @file xl_i2c.h * @author software group * @brief This file contains all the functions prototypes for the I2C * firmware library. ****************************************************************************** * @attention * * 2019 by Chipways Communications,Inc. All Rights Reserved. * This software is supplied under the terms of a license * agreement or non-disclosure agreement with Chipways. * Passing on and copying of this document,and communication * of its contents is not permitted without prior written * authorization. * *

© COPYRIGHT 2019 Chipways

****************************************************************************** */ #ifndef __XL_I2C_H__ #define __XL_I2C_H__ #ifdef __cplusplus extern "C" { #endif /* Define to prevent recursive inclusion -------------------------------------*/ #include "XL6600.h" /* Register define ------------------------------------------------------------*/ /* I2C_CR Bit Fields */ #define I2C_CR_ME_MASK 0x1u #define I2C_CR_ME_SHIFT 0 #define I2C_CR_SPEED_MASK 0x6u #define I2C_CR_SPEED_SHIFT 2 #define I2C_CR_SAD_MASK 0x8u #define I2C_CR_SAD_SHIFT 3 #define I2C_CR_MAD_MASK 0x10u #define I2C_CR_MAD_SHIFT 4 #define I2C_CR_RE_MASK 0x20u #define I2C_CR_RE_SHIFT 5 #define I2C_CR_SD_MASK 0x40u #define I2C_CR_SD_SHIFT 6 /* I2C_TAR Bit Fields */ #define I2C_TAR_TAD_MASK 0x3FFu #define I2C_TAR_TAD_SHIFT 0 #define I2C_TAR_GOS_MASK 0x400u #define I2C_TAR_GOS_SHIFT 10 #define I2C_TAR_SPECIAL_MASK 0x800u #define I2C_TAR_SPECIAL_SHIFT 11 /* I2C_SAR Bit Fields */ #define I2C_SAR_SAD_MASK 0x3FFu #define I2C_SAR_SAD_SHIFT 0 /* I2C_HSMA Bit Fields */ #define I2C_HSMA_HSMC_MASK 0x7u #define I2C_HSMA_HSMC_SHIFT 0 /* I2C_DBC Bit Fields */ #define I2C_DBC_DAT_MASK 0xFFu #define I2C_DBC_DAT_SHIFT 0 #define I2C_DBC_CMD_MASK 0x100u #define I2C_DBC_CMD_SHIFT 8 #define I2C_DBC_STOP_MASK 0x200u #define I2C_DBC_STOP_SHIFT 9 #define I2C_DBC_RESTART_MASK 0x400u #define I2C_DBC_RESTART_SHIFT 10 /* I2C_SSCH Bit Fields */ #define I2C_SSCH_HCNT_MASK 0xFFFFu #define I2C_SSCH_HCNT_SHIFT 0 /* I2C_SSCL Bit Fields */ #define I2C_SSCL_LCNT_MASK 0xFFFFu #define I2C_SSCL_LCNT_SHIFT 0 /* I2C_FSCH Bit Fields */ #define I2C_FSCH_HCNT_MASK 0xFFFFu #define I2C_FSCH_HCNT_SHIFT 0 /* I2C_FSCL Bit Fields */ #define I2C_FSCL_LCNT_MASK 0xFFFFu #define I2C_FSCL_LCNT_SHIFT 0 /* I2C_HSCH Bit Fields */ #define I2C_HSCH_HCNT_MASK 0xFFFFu #define I2C_HSCH_HCNT_SHIFT 0 /* I2C_HSCL Bit Fields */ #define I2C_HSCL_LCNT_MASK 0xFFFFu #define I2C_HSCL_LCNT_SHIFT 0 /* I2C_IS Bit Fields */ #define I2C_IS_RU_MASK 0x1u #define I2C_IS_RU_SHIFT 0 #define I2C_IS_RO_MASK 0x2u #define I2C_IS_RO_SHIFT 1 #define I2C_IS_RF_MASK 0x4u #define I2C_IS_RF_SHIFT 2 #define I2C_IS_TO_MASK 0x8u #define I2C_IS_TO_SHIFT 3 #define I2C_IS_TEMP_MASK 0x10u #define I2C_IS_TEMP_SHIFT 4 #define I2C_IS_RDREQ_MASK 0x20u #define I2C_IS_RDREQ_SHIFT 5 #define I2C_IS_TABT_MASK 0x40u #define I2C_IS_TABT_SHIFT 6 #define I2C_IS_RD_MASK 0x80u #define I2C_IS_RD_SHIFT 7 #define I2C_IS_ACT_MASK 0x100u #define I2C_IS_ACT_SHIFT 8 #define I2C_IS_STPD_MASK 0x200u #define I2C_IS_STPD_SHIFT 9 #define I2C_IS_STATD_MASK 0x400u #define I2C_IS_STATD_SHIFT 10 #define I2C_IS_GC_MASK 0x800u #define I2C_IS_GC_SHIFT 11 /* I2C_INTRM Bit Fields */ #define I2C_INTRM_RU_MASK 0x1u #define I2C_INTRM_RU_SHIFT 0 #define I2C_INTRM_RO_MASK 0x2u #define I2C_INTRM_RO_SHIFT 1 #define I2C_INTRM_RF_MASK 0x4u #define I2C_INTRM_RF_SHIFT 2 #define I2C_INTRM_TO_MASK 0x8u #define I2C_INTRM_TO_SHIFT 3 #define I2C_INTRM_TEMP_MASK 0x10u #define I2C_INTRM_TEMP_SHIFT 4 #define I2C_INTRM_RDREQ_MASK 0x20u #define I2C_INTRM_RDREQ_SHIFT 5 #define I2C_INTRM_TABT_MASK 0x40u #define I2C_INTRM_TABT_SHIFT 6 #define I2C_INTRM_RD_MASK 0x80u #define I2C_INTRM_RD_SHIFT 7 #define I2C_INTRM_ACT_MASK 0x100u #define I2C_INTRM_ACT_SHIFT 8 #define I2C_INTRM_STPD_MASK 0x200u #define I2C_INTRM_STPD_SHIFT 9 #define I2C_INTRM_STATD_MASK 0x400u #define I2C_INTRM_STATD_SHIFT 10 #define I2C_INTRM_GC_MASK 0x800u #define I2C_INTRM_GC_SHIFT 11 /* I2C_RIS Bit Fields */ #define I2C_RIS_RU_MASK 0x1u #define I2C_RIS_RU_SHIFT 0 #define I2C_RIS_RO_MASK 0x2u #define I2C_RIS_RO_SHIFT 1 #define I2C_RIS_RF_MASK 0x4u #define I2C_RIS_RF_SHIFT 2 #define I2C_RIS_TO_MASK 0x8u #define I2C_RIS_TO_SHIFT 3 #define I2C_RIS_TEMP_MASK 0x10u #define I2C_RIS_TEMP_SHIFT 4 #define I2C_RIS_RDREQ_MASK 0x20u #define I2C_RIS_RDREQ_SHIFT 5 #define I2C_RIS_TABT_MASK 0x40u #define I2C_RIS_TABT_SHIFT 6 #define I2C_RIS_RD_MASK 0x80u #define I2C_RIS_RD_SHIFT 7 #define I2C_RIS_ACT_MASK 0x100u #define I2C_RIS_ACT_SHIFT 8 #define I2C_RIS_STPD_MASK 0x200u #define I2C_RIS_STPD_SHIFT 9 #define I2C_RIS_STATD_MASK 0x400u #define I2C_RIS_STATD_SHIFT 10 #define I2C_RIS_GC_MASK 0x800u #define I2C_RIS_GC_SHIFT 11 /* I2C_RXTL Bit Fields */ #define I2C_RXTL_RFTL_MASK 0xFFu #define I2C_RXTL_RFTL_SHIFT 0 /* I2C_TXTL Bit Fields */ #define I2C_TXTL_TFTL_MASK 0xFFu #define I2C_TXTL_TFTL_SHIFT 0 /* I2C_CCI Bit Fields */ #define I2C_CCI_CI_MASK 0x1u #define I2C_CCI_CI_SHIFT 0 /* I2C_CRU Bit Fields */ #define I2C_CRU_CRUI_MASK 0x1u #define I2C_CRU_CRUI_SHIFT 0 /* I2C_CRO Bit Fields */ #define I2C_CRO_CROI_MASK 0x1u #define I2C_CRO_CROI_SHIFT 0 /* I2C_CTO Bit Fields */ #define I2C_CTO_CTOI_MASK 0x1u #define I2C_CTO_CTOI_SHIFT 0 /* I2C_CRR Bit Fields */ #define I2C_CRR_CRRI_MASK 0x1u #define I2C_CRR_CRRI_SHIFT 0 /* I2C_CTXA Bit Fields */ #define I2C_CTXA_CTABTI_MASK 0x1u #define I2C_CTXA_CTABTI_SHIFT 0 /* I2C_CRD Bit Fields */ #define I2C_CRD_CRDI_MASK 0x1u #define I2C_CRD_CRDI_SHIFT 0 /* I2C__CACT Bit Fields */ #define I2C_CACT_CACT_MASK 0x1u #define I2C_CACT_CACT_SHIFT 0 /* I2C_CSTOP Bit Fields */ #define I2C_CSTOP_CSTPD_MASK 0x1u #define I2C_CSTOP_CSTPD_SHIFT 0 /* I2C_CSTART Bit Fields */ #define I2C_CSTART_CSTATD_MASK 0x1u #define I2C_CSTART_CSTATD_SHIFT 0 /* I2C_CGC Bit Fields */ #define I2C_CGC_CGC_MASK 0x1u #define I2C_CGC_CGC_SHIFT 0 /* I2C_ENABLE Bit Fields */ #define I2C_ENABLE_EN_MASK 0x1u #define I2C_ENABLE_EN_SHIFT 0 /* I2C_STATUS Bit Fields */ #define I2C_STATUS_ACT_MASK 0x1u #define I2C_STATUS_ACT_SHIFT 0 #define I2C_STATUS_TFNF_MASK 0x2u #define I2C_STATUS_TFNF_SHIFT 1 #define I2C_STATUS_TFE_MASK 0x4u #define I2C_STATUS_TFE_SHIFT 2 #define I2C_STATUS_RFNE_MASK 0x8u #define I2C_STATUS_RFNE_SHIFT 3 #define I2C_STATUS_RFF_MASK 0x10u #define I2C_STATUS_RFF_SHIFT 4 #define I2C_STATUS_MACT_MASK 0x20u #define I2C_STATUS_MACT_SHIFT 5 #define I2C_STATUS_SACT_MASK 0x40u #define I2C_STATUS_SACT_SHIFT 6 /* I2C_TXFLR Bit Fields */ #define I2C_TXFLR_TXFL_MASK 0xFu #define I2C_TXFLR_TXFL_SHIFT 0 /* I2C_RXFLR Bit Fields */ #define I2C_RXFLR_RXFL_MASK 0xFu #define I2C_RXFLR_RXFL_SHIFT 0 /* I2C_TXAS Bit Fields */ #define I2C_TXAS_A7ADN_MASK 0x1u #define I2C_TXAS_A7ADN_SHIFT 0 #define I2C_TXAS_A10AD1N_MASK 0x2u #define I2C_TXAS_A10AD1N_SHIFT 1 #define I2C_TXAS_A10AD2N_MASK 0x4u #define I2C_TXAS_A10AD2N_SHIFT 2 #define I2C_TXAS_ATXDN_MASK 0x8u #define I2C_TXAS_ATXDN_SHIFT 3 #define I2C_TXAS_AGCN_MASK 0x10u #define I2C_TXAS_AGCN_SHIFT 4 #define I2C_TXAS_AGCR_MASK 0x20u #define I2C_TXAS_AGCR_SHIFT 5 #define I2C_TXAS_AHSA_MASK 0x40u #define I2C_TXAS_AHSA_SHIFT 6 #define I2C_TXAS_ASBA_MASK 0x80u #define I2C_TXAS_ASBA_SHIFT 7 #define I2C_TXAS_AHSNS_MASK 0x100u #define I2C_TXAS_AHSNS_SHIFT 8 #define I2C_TXAS_ASBNS_MASK 0x200u #define I2C_TXAS_ASBNS_SHIFT 9 #define I2C_TXAS_A10BNS_MASK 0x400u #define I2C_TXAS_A10BNS_SHIFT 10 #define I2C_TXAS_AMD_MASK 0x800u #define I2C_TXAS_AMD_SHIFT 11 #define I2C_TXAS_AL_MASK 0x1000u #define I2C_TXAS_AL_SHIFT 12 #define I2C_TXAS_AST_MASK 0x2000u #define I2C_TXAS_AST_SHIFT 13 #define I2C_TXAS_ASA_MASK 0x4000u #define I2C_TXAS_ASA_SHIFT 14 #define I2C_TXAS_ASI_MASK 0x8000u #define I2C_TXAS_ASI_SHIFT 15 /* I2C_SDAS Bit Fields */ #define I2C_SDAS_SDAS_MASK 0xFFu #define I2C_SDAS_SDAS_SHIFT 0 /* I2C_AGC Bit Fields */ #define I2C_AGC_ACKGC_MASK 0x1u #define I2C_AGC_ACKGC_SHIFT 0 /* I2C_ES Bit Fields */ #define I2C_ES_ENS_MASK 0x1u #define I2C_ES_ENS_SHIFT 0 #define I2C_ES_SROA_MASK 0x2u #define I2C_ES_SROA_SHIFT 1 #define I2C_ES_SFFF_MASK 0x4u #define I2C_ES_SFFF_SHIFT 2 /** I2C - Register Layout Typedef */ typedef struct { __IO uint32_t CR; /**