/**
  ******************************************************************************
  * @file     xl_dma.c
  * @author   xu.wang
  * @version  4.5.2
  * @date     Fri Mar 26 17:29:12 2021
  * @brief    This file provide function about DMA firmware program 
  ******************************************************************************
  * @attention
	*
  * 2019 by Chipways Communications,Inc. All Rights Reserved.
  * This software is supplied under the terms of a license
  * agreement or non-disclosure agreement with Chipways.
  * Passing on and copying of this document,and communication
  * of its contents is not permitted without prior written
  * authorization.
  *
  * <h2><center>&copy; COPYRIGHT 2019 Chipways</center></h2>
  ******************************************************************************
  */

#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/* Includes ---------------------------------------------------------------*/
#include "xl_dma.h"

/** @addtogroup XL6600_StdPeriph_Driver
  * @{
  */

/** @defgroup DMA   DMA Module
  * @brief DMA Driver Modules Library
  * @{
  */
	
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/	
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
	
/** @defgroup DMA_Private_Functions 
* @{
*/ 

/**
 * @brief  ÉèÖÃDMA ͨµÀµÄ³õʼ»¯
 * @param  DMAx: DMAÍâÉè
 * @param  DMA_InitStruct: DMA³õʼ»¯²ÎÊý½á¹¹Ìå
 * @retval None
 */
void DMA_ChannelInit(const DMA_InitTypeDef *DMA_InitStruct)
{
	uint32_t temp;
	
	temp =	(uint32_t)(((uint32_t)DMA_InitStruct->TargetBurst<<DMA_DMACTRLC_DBURSTC_SHIFT)    | ((uint32_t)DMA_InitStruct->SourceBurst<<DMA_DMACTRLC_SBURSTC_SHIFT) | \
					((uint32_t)DMA_InitStruct->TargetWidth<<DMA_DMACTRLC_DWIDTHC_SHIFT)    | ((uint32_t)DMA_InitStruct->SourceWidth<<DMA_DMACTRLC_SWIDTHC_SHIFT) |  \
					((uint32_t)DMA_InitStruct->TransferSize<<DMA_DMACTRLC_TRANSIZEC_SHIFT) | ((uint32_t)DMA_InitStruct->FlowControl<<DMA_DMACTRLC_FLOWCTRLC_SHIFT) |  \
					((uint32_t)DMA_InitStruct->TargetPerID<<DMA_DMACTRLC_DSTPERC_SHIFT)    | ((uint32_t)DMA_InitStruct->SourcePerID<<DMA_DMACTRLC_SRCPERC_SHIFT) |  \
					((uint32_t)DMA_InitStruct->TargetAddrInc<<DMA_DMACTRLC_DSTINCC_SHIFT)  | ((uint32_t)DMA_InitStruct->SourceAddrInc<<DMA_DMACTRLC_SRCINCC_SHIFT));
	
	DMA->DMACHANREG[DMA_InitStruct->chan].DMACTRLC = temp;
}
/**
 * @brief  DMAʹÄÜ
 * @param  DMAx: DMAÍâÉè
 * @param  NewState: ״̬ѡÔñ
 *		Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
 *			@arg ENABLE £ºÊ¹ÄÜ
 *			@arg DISENABLE £ºÊ§ÄÜ
 * @retval None
 */
void DMA_Enable(FunctionalState NewState)
{
	if(NewState != DISABLE )
	{
			DMA->DMAEN = 0x444D4145;
	}
	else 
	{
			DMA->DMASRST = 0x53525354;
	}
}
/**
 * @brief  DMAͨµÀʹÄÜ
 * @param  DMAx: DMAÍâÉè
 * @param  Channel: DMAͨµÀ
 *		Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
 *			@arg DMA_Channel_0 £ºDMAͨµÀ0
 *			@arg DMA_Channel_1 £ºDMAͨµÀ1
 *			@arg DMA_Channel_2 £ºDMAͨµÀ2
 *			@arg DMA_Channel_3 £ºDMAͨµÀ3
 * @param  NewState: ״̬ѡÔñ
 *		Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
 *			@arg ENABLE £ºÊ¹ÄÜ
 *			@arg DISENABLE £ºÊ§ÄÜ
 * @retval None
 */

void DMA_ChannelEnableCmd(uint8_t Channel,FunctionalState NewState)
{
	if(NewState != DISABLE )
	{
			DMA->DMACHANREG[Channel].DMACTRLC |= DMA_DMAEN_DMAEN_MASK;
	}
	else 
	{
			DMA->DMACHANREG[Channel].DMACTRLC &= ~DMA_DMAEN_DMAEN_MASK;
	}
}
/**
 * @brief  DMAÉèÖÃÔ´µØÖ·
 * @param  DMAx: DMAÍâÉè
 * @param  Channel: DMAͨµÀ
 *		Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
 *			@arg DMA_Channel_0 £ºDMAͨµÀ0
 *			@arg DMA_Channel_1 £ºDMAͨµÀ1
 *			@arg DMA_Channel_2 £ºDMAͨµÀ2
 *			@arg DMA_Channel_3 £ºDMAͨµÀ3
 * @param  address: DMAÔ´µØÖ·
 * @retval None
 */
void DMA_SetSourceAddress(uint8_t Channel,uint32_t address)
{
	DMA->DMACHANREG[Channel].DMASRCADDRC = address;
}
/**
 * @brief  DMAÉèÖÃÄ¿±êµØÖ·
 * @param  DMAx: DMAÍâÉè
 * @param  Channel: DMAͨµÀ
 *		Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
 *			@arg DMA_Channel_0 £ºDMAͨµÀ0
 *			@arg DMA_Channel_1 £ºDMAͨµÀ1
 *			@arg DMA_Channel_2 £ºDMAͨµÀ2
 *			@arg DMA_Channel_3 £ºDMAͨµÀ3
 * @param  address: DMAÄ¿±êµØÖ·
 * @retval None
 */
void DMA_SetTargetAddress(uint8_t Channel,uint32_t address)
{
	DMA->DMACHANREG[Channel].DMADSTADDRC = address;
}

/**
 * @brief  DMAÉèÖÃÄ¿±êµØÖ·
 * @param  DMAx: DMAÍâÉè
 * @param  channel: DMAͨµÀ
 *		Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
 *			@arg DMA_Channel_0 £ºDMAͨµÀ0
 *			@arg DMA_Channel_1 £ºDMAͨµÀ1
 *			@arg DMA_Channel_2 £ºDMAͨµÀ2
 *			@arg DMA_Channel_3 £ºDMAͨµÀ3
 * @param  address: DMAÄ¿±êµØÖ·
 * @retval None
 */
void DMA_SetTransferSize(uint8_t channel,uint16_t len)
{
	DMA->DMACHANREG[channel].DMACTRLC |= (uint32_t)((uint32_t)len<<DMA_DMACTRLC_TRANSIZEC_SHIFT);
}

/**
 * @brief  DMAµÃµ½Í¨µÀ״̬
 * @param  DMAx: DMAÍâÉè
 * @param  Channel: DMAͨµÀ
 *		Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
 *			@arg DMA_Channel_0 £ºDMAͨµÀ0
 *			@arg DMA_Channel_1 £ºDMAͨµÀ1
 *			@arg DMA_Channel_2 £ºDMAͨµÀ2
 *			@arg DMA_Channel_3 £ºDMAͨµÀ3
 * @retval None
 */
uint8_t DMA_GetChannelStatus(uint8_t Channel)
{
	uint8_t temp;
	temp = (uint8_t)(DMA->DMACHANREG[Channel].DMASTATUSC & 0x00000001u);
	return temp; 
}
/**
 * @brief  DMAµÃµ½´«ÊäÊý¾ÝµÄ³¤¶È
 * @param  DMAx: DMAÍâÉè
 * @param  Channel: DMAͨµÀ
 *		Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
 *			@arg DMA_Channel_0 £ºDMAͨµÀ0
 *			@arg DMA_Channel_1 £ºDMAͨµÀ1
 *			@arg DMA_Channel_2 £ºDMAͨµÀ2
 *			@arg DMA_Channel_3 £ºDMAͨµÀ3
 * @retval None
 */
uint16_t DMA_GetChanTransferDataLen(uint8_t Channel)
{
	uint16_t temp;
	temp = (uint16_t)(DMA->DMACHANREG[Channel].DMASTATUSC & 0x000007FEu);
	return temp>>1u; 
}
/**
 * @brief  DMAµÃµ½ÖжÏ״̬
 * @param  DMAx: DMAÍâÉè
 * @param  DMA_InterruptStatusType: DMAÖжÏÔ´
 *		Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
 *			@arg DMA_Channel0_Err £ºDMAͨµÀ0´íÎóÖжÏ
 *			@arg DMA_Channel1_Err £ºDMAͨµÀ1´íÎóÖжÏ
 *			@arg DMA_Channel2_Err £ºDMAͨµÀ2´íÎóÖжÏ
 *			@arg DMA_Channel3_Err £ºDMAͨµÀ3´íÎóÖжÏ
 *			@arg DMA_Channel0_TransferFinish £ºDMAͨµÀ0´«ÊäÍê³ÉÖжÏ
 *			@arg DMA_Channel1_TransferFinish £ºDMAͨµÀ1´«ÊäÍê³ÉÖжÏ
 *			@arg DMA_Channel2_TransferFinish £ºDMAͨµÀ2´«ÊäÍê³ÉÖжÏ
 *			@arg DMA_Channel3_TransferFinish £ºDMAͨµÀ3´«ÊäÍê³ÉÖжÏ
 *			@arg DMA_ClearALL_Status £ºDMAËùÓÐÖжÏ
 * @retval None
 */

uint8_t DMA_GetInterruptStatus(uint8_t DMA_InterruptStatusType)
{
	uint8_t DMAStatusTemp;

	/* Get all the Line Control status */
	DMAStatusTemp =(uint8_t) DMA->DMAINTSTATUS;

	/* get the selected Line Control status */
	return (DMAStatusTemp & (uint8_t)((uint32_t)1u<<DMA_InterruptStatusType));
}

/**
 * @brief  DMAÇå³ýÖжϱêÖ¾
 * @param  DMAx: DMAÍâÉè
 * @param  DMA_InterruptStatusType: DMAÖжÏÔ´
 *		Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
 *			@arg DMA_Channel0_Err £ºDMAͨµÀ0´íÎóÖжÏ
 *			@arg DMA_Channel1_Err £ºDMAͨµÀ1´íÎóÖжÏ
 *			@arg DMA_Channel2_Err £ºDMAͨµÀ2´íÎóÖжÏ
 *			@arg DMA_Channel3_Err £ºDMAͨµÀ3´íÎóÖжÏ
 *			@arg DMA_Channel0_TransferFinish £ºDMAͨµÀ0´«ÊäÍê³ÉÖжÏ
 *			@arg DMA_Channel1_TransferFinish £ºDMAͨµÀ1´«ÊäÍê³ÉÖжÏ
 *			@arg DMA_Channel2_TransferFinish £ºDMAͨµÀ2´«ÊäÍê³ÉÖжÏ
 *			@arg DMA_Channel3_TransferFinish £ºDMAͨµÀ3´«ÊäÍê³ÉÖжÏ
 *			@arg DMA_ClearALL_Status £ºDMAËùÓÐÖжÏ
 * @retval None
 */

void DMA_ClearInterruptStatus(const uint8_t DMA_InterruptStatusType)
{
	if(DMA_InterruptStatusType == (uint8_t)DMA_ClearALL_Status)
	{
		DMA->DMAINTSTATUS = 0x000000FFu;
	}
	else
	{
		DMA->DMAINTSTATUS |= (uint32_t)1u << DMA_InterruptStatusType;
	}
}
/**
 * @brief  DMAʹÄÜÖжÏ
 * @param  DMAx: DMAÍâÉè
 * @param  DMA_InterruptStatusType: DMAÖжÏÔ´
 *		Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
 *			@arg DMA_Channel0_Err_Mask £ºDMAͨµÀ0´íÎóÖжÏÆÁ±Î
 *			@arg DMA_Channel1_Err_Mask £ºDMAͨµÀ1´íÎóÖжÏÆÁ±Î
 *			@arg DMA_Channel2_Err_Mask £ºDMAͨµÀ2´íÎóÖжÏÆÁ±Î
 *			@arg DMA_Channel3_Err_Mask £ºDMAͨµÀ3´íÎóÖжÏÆÁ±Î
 *			@arg DMA_Channel0_TransferFinish_Mask £ºDMAͨµÀ0´«ÊäÍê³ÉÖжÏÆÁ±Î
 *			@arg DMA_Channel1_TransferFinish_Mask £ºDMAͨµÀ1´«ÊäÍê³ÉÖжÏÆÁ±Î
 *			@arg DMA_Channel2_TransferFinish_Mask £ºDMAͨµÀ2´«ÊäÍê³ÉÖжÏÆÁ±Î
 *			@arg DMA_Channel3_TransferFinish_Mask £ºDMAͨµÀ3´«ÊäÍê³ÉÖжÏÆÁ±Î
 * @param  NewState: ״̬ѡÔñ
 *		Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
 *			@arg ENABLE £ºÊ¹ÄÜ
 *			@arg DISENABLE £ºÊ§ÄÜ
 * @retval None
 */

void DMA_InterruptEnable(uint8_t DMA_InterruptMaskType,FunctionalState NewState)
{
	uint32_t itenable;

	/* Get the interrupt enable index */
	itenable = ((uint32_t)1u << DMA_InterruptMaskType);
	if(NewState != DISABLE )
	{
		/* Enable the selected UART interrupts */
		DMA->DMAINTMASK |= itenable ;
	}
	else 
	{
		DMA->DMAINTMASK &= ~itenable;
	}
}

/**
 * @brief  DMAÍâÉèÇëÇó״̬
 * @param  DMAx: DMAÍâÉè
 * @param  DMA_Peripheral_ResquestType: ÍâÉèÇëÇó״̬
 *		Õâ¸ö²ÎÊý¿ÉÒÔÈ¡ÏÂÃæµÄÖµ:
 *			@arg DMA_SPI1_Tx_Req £ºSPI1·¢ËÍÊý¾ÝÇëÇó״̬
 *			@arg DMA_SPI1_Rx_Req £ºSPI1½ÓÊÕÊý¾ÝÇëÇó״̬
 *			@arg DMA_SPI0_Tx_Req £ºSPI0·¢ËÍÊý¾ÝÇëÇó״̬
 *			@arg DMA_SPI0_Rx_Req £ºSPI0½ÓÊÕÊý¾ÝÇëÇó״̬
 *			@arg DMA_UART0_Tx_Req £ºUART0·¢ËÍÊý¾ÝÇëÇó״̬
 *			@arg DMA_UART0_Rx_Req £ºUART0½ÓÊÕÊý¾ÝÇëÇó״̬
 *			@arg DMA_UART1_Tx_Req £ºUART1·¢ËÍÊý¾ÝÇëÇó״̬
 *			@arg DMA_UART1_Rx_Req £ºUART1½ÓÊÕÊý¾ÝÇëÇó״̬
 *			@arg DMA_UART2_Tx_Req £ºUART2·¢ËÍÊý¾ÝÇëÇó״̬
 *			@arg DMA_UART2_Rx_Req £ºUART2½ÓÊÕÊý¾ÝÇëÇó״̬
 *			@arg DMA_ADC_Tx_Req £ºADCÊý¾Ý»º´æ״̬
 *			@arg DMA_ADC_Rx_Req £ºADCת»»Êý¾Ý¾ÍÐ÷״̬
 * @retval None
 */

uint32_t DMA_GetPeripheralResquestStatus(const uint8_t DMA_Peripheral_ResquestType)
{
	uint32_t DMAPeripheral_Resquest;
	
	/* Get all the Line Control status */
	DMAPeripheral_Resquest = DMA->DMAPERREQ;

	/* get the selected Line Control status */
	return (uint32_t)(DMAPeripheral_Resquest & ((uint32_t)1u<<DMA_Peripheral_ResquestType));
}
/**
  * @}
  */

/**
  * @}
  */

/**
  * @}
  */
#ifdef __cplusplus
}
#endif /* __cplusplus */